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freescale semiconductor, inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. document number: mc33903_4_5 rev. 9.0, 2/2012 freescale semiconductor ? technical data ? freescale semiconductor, inc., 2010 - 2012. all rights reserved. sbc gen2 with can high speed and lin interface the 33903/4/5 is the second generatio n family of the system basis chip (sbc). it combines several features and enhances present module designs. the device works as an advanced power management unit for the mcu with additional integrated circuits such as sensors and can transceivers. it has a built-in enhanced high-speed can interface (iso11898-2 and -5) with local and bus failure diagnostics, protection, and fail-saf e operation modes. the sbc may include zero, one or two lin 2.1 inte rfaces with lin outp ut pin switches. it includes up to four wake-up input pins that can also be configured as output drivers for flexibility. this device implements multiple lo w-power (lp) modes, with very low-current consumption. in addition , the device is part of a family concept where pin compatibility adds versatility to module design. the 33903/4/5 also implements an innovative and advanced fail-safe state machine and concept solution. features ? voltage regulator for mcu, 5.0 or 3.3 v, part number selectable, with possibility of usage external pnp to extend current capability and share power dissipation ? voltage, current, and temperature protection ? extremely low quiescent current in lp modes ? fully-protected embedded 5.0 v regulator for the can driver ? multiple under-voltage detections to address various mcu specifications and system o peration modes (i.e. cranking) ? auxiliary 5.0 or 3.3 v spi configurable regulator, for additional ics, with over-current detection and under-voltage protection ? mux output pin for device internal analog signal monitoring and power supply monitoring ? advanced spi, mcu, ecu power supply, and critical pins diagnostics and monitoring. ? multiple wake-up sources in lp modes: can or lin bus, ? i/o transition, automatic timer, spi message, and v dd over-current detection. ? iso11898-5 high-speed can interface compatibility for baud rates of 40 kb/s to 1.0 mb/s ? scalable product family of devices ranging from 0 to 2 lins which are ? compatible to j2602-2 and lin 2.1 33903/ 33903/4/5 ek suffix (pb-free) 98asa10556d 32-pin soic ek suffix (pb-free) 98asa10506d 54-pin soic system basis chip
analog integrated circuit device data ? 2 freescale semiconductor 33903/4/5 table of contents table of contents simplified application diagrams ............................................................................................... .................. 3 device variations ............................................................................................................. .......................... 7 internal block diagrams ........ ............................................................................................... ...................... 9 pin connections ............................................................................................................... ........................ 11 electrical characteristics ... ................................................................................................. ...................... 17 maximum ratings ............................................................................................................... ................... 17 static electrical characterist ics ............................................................................................. ................ 19 dynamic electrical characteristics .................. .......................................................................... ............ 27 timing diagrams ............................................................................................................... .................... 30 functional description ........................................................................................................ ...................... 35 introduction .................................................................................................................. .......................... 35 functional pin description .................................................................................................... ................. 35 functional device operation ................................................................................................... ................. 39 mode and state description .................................................................................................... .............. 39 lp modes ...................................................................................................................... ........................ 40 state diagram ................................................................................................................. ....................... 41 mode change ................................................................................................................... ..................... 42 watchdog operation ............................................................................................................ .................. 42 functional block operation versus mode ........................................................................................ ..... 44 illustration of device mode transitions. ...................................................................................... ........... 45 cyclic sense operation during lp modes ........................................................................................ .... 47 behavior at power up and power down ............... ............................................................................ .... 49 fail-safe operation ........................................................................................................... ........................ 51 can interface ................................................................................................................. ....................... 55 can interface description ..................................................................................................... ................ 55 can bus fault diagnostic ...................................................................................................... ............... 58 lin block ..................................................................................................................... ............................. 61 lin interface description ..................................................................................................... .................. 61 lin operational modes ......................................................................................................... ................. 61 serial peripheral interface ................................................................................................... ..................... 63 high level overview ........................................................................................................... ................... 63 detail operation .............................................................................................................. ....................... 64 detail of control bits and register mapping ...... ............................................................................. ...... 67 flags and device status ....................................................................................................... ................. 84 typical applications .......................................................................................................... ....................... 91 packaging ..................................................................................................................... ........................... 99
analog integrated circuit device data ? freescale semiconductor 3 33903/4/5 simplified application diagrams simplified appl ication diagrams figure 1. 33905d simplified application diagram figure 2. 33905s simplified application diagram cs sclk mosi int 5v-can v sup1 i/o-0 i/o-1 miso rxd txd canl canh gnd rst dbg v dd split v bat v b q1* d1 v baux safe rxd-l1 txd-l1 lin-term 1 lin-1 v e q2 (5.0 v/3.3 v) v dd v sup2 v aux v caux lin-term 2 lin-2 rxd-l2 txd-l2 mux-out 33905d mcu spi a/d can bus lin bus lin bus vsense * = optional cs sclk mosi int 5v-can v sup1 i/o-0 i/o-1 miso rxd txd canl canh gnd rst dbg v dd split v bat v b q1* d1 v baux safe rxd-l txd-l lin-t lin v e q2 (5.0 v/3.3 v) v dd v sup2 v aux v caux i/o-3 mux-out 33905s mcu spi a/d can bus lin bus vsense v bat * = optional
analog integrated circuit device data ? 4 freescale semiconductor 33903/4/5 simplified application diagrams figure 3. 33904 simplified application diagram figure 4. 33903 simplified application diagram 33904 cs sclk mosi int 5v-can v sup1 i/o-0 i/o-1 miso rxd txd canl canh gnd rst dbg v dd split v bat v b q1* d1 v baux safe i/o-3 v e q2 (5.0 v/3.3 v) v dd v sup2 v aux v caux i/o-2 mux-out mcu spi a/d can bus vsense v bat * = optional cs sclk mosi int 5v-can vsup2 i/o-0 miso rxd txd canl canh gnd rst dbg vdd split v bat d1 v dd 33903 mcu spi can bus safe vsup1
analog integrated circuit device data ? freescale semiconductor 5 33903/4/5 simplified application diagrams figure 5. 33903d simplified application diagram figure 6. 33903s simplified application diagram cs sclk mosi int 5v-can v sup io-0 miso rxd txd canl canh gnd rst dbg v dd split v bat v b q1* d1 safe rxd-l1 txd-l1 lin-t1/i/o-2 lin-1 v e v dd lin-t2/io-3 lin-2 rxd-l2 txd-l2 mux-out 33903d mcu spi a/d can bus lin bus lin bus vsense * = optional cs sclk mosi int 5v-can v sup io-0 miso rxd txd canl canh gnd rst dbg v dd split v bat v b q1* d1 safe rxd-l1 txd-l1 lin-t1/i/o-2 lin-1 v e v dd mux-out 33903s mcu spi a/d can bus lin bus vsense * = optional i/o-3 v bat
analog integrated circuit device data ? 6 freescale semiconductor 33903/4/5 simplified application diagrams figure 7. 33903p simplified application diagram cs sclk mosi int 5v-can v sup io-0 miso rxd txd canl canh gnd rst dbg v dd split v bat v b q1* d1 safe v e v dd mux-out 33903p mcu spi a/d can bus vsense * = optional i/o-3 v bat v bat i/o-2
analog integrated circuit device data ? freescale semiconductor 7 33903/4/5 device variations device variations table 1. mc33905 device variations - (all devices rated at t a = -40 to 125 c) freescale part number version (1) , (2) v dd output voltage lin interface(s) wake-up input / lin master termination package v aux v sense mux mc33905d (dual lin) mcz33905bd3ek/r2 b 3.3 v 2 2 wake-up + 2 lin terms or 3 wake-up + 1 lin terms or 4 wake-up + no lin terms soic 54 pin exposed pad yes yes yes mcz33905cd3ek/r2 c mcz33905d5ek/r2 5.0 v mcz33905bd5ek/r2 b mcz33905cd5ek/r2 c mc33905s (single lin) mcz33905bs3ek/r2 b 3.3 v 1 3 wake-up + 1 lin terms or 4 wake-up + no lin terms yes yes yes mcz33905cs3ek/r2 c mcz33905s5ek/r2 5.0 v mcz33905bs5ek/r2 b mcz33905cs5ek/r2 c notes 1. design changes in the ?b? version resolved v sup slow ramp up issues, enhanced device curre nt consumption and improved oscillator stability. ?b? version has an errata linked to the spi operation. 2. ?c? versions are recommended for new designs . design changes in the ?c? version resolv e the spi deviation of all prior versio ns, and does not have the rxd short to ground detection feature. table 2. mc33904 device variations - (all devices rated at t a = -40 to 125 c) freescale part number version (3) , (4) v dd output voltage lin interface(s) wake-up input / lin master termination package v aux v sense mux mc33904 mcz33904b3ek/r2 b 3.3 v 0 4 wake-up soic 32 pin exposed pad yes yes yes mcz33904c3ek/r2 c mcz33904a5ek/r2 a 5.0 v mcz33904b5ek/r2 b mcz33904c5ek/r2 c notes 3. design changes in the ?b? version resolved v sup slow ramp up issues, enhanced device curre nt consumption and improved oscillator stability. ?b? version has an errata linked to the spi operation. 4. ?c? versions are recommended for new designs . design changes in the ?c? version resolv e the spi deviation of all prior versio ns, and does not have the rxd short to ground detection feature.
analog integrated circuit device data ? 8 freescale semiconductor 33903/4/5 device variations table 3. mc33903 device variations - (all devices rated at t a = -40 to 125 c) freescale part number version (6) , (7) v dd output voltage lin interface(s) wake-up input / lin master termination package v aux v sense mux mc33903 mcz33903b3ek/r2 b 3.3 v (5) 0 1 wake-up soic 32 pin exposed pad no no no mcz33903c3ek/r2 c mcz33903b5ek/r2 b 5.0 v (5) mcz33903c5ek/r2 c mc33903d (dual lin) mcz33903bd3ek/r2 b 3.3 v 2 1 wake-up + 2 lin terms or 2 wake-up + 1 lin terms or 3 wake-up + no lin terms soic 32 pin exposed pad no yes yes mcz33903cd3ek/r2 c mcz33903bd5ek/r2 b 5.0 v mcz33903cd5ek/r2 c mc33903s (single lin) mcz33903bs3ek/r2 b 3.3 v 1 2 wake-up + 1 lin terms or 3 wake-up + no lin terms soic 32 pin exposed pad no yes yes mcz33903cs3ek/r2 c mcz33903bs5ek/r2 b 5.0 v mcz33903cs5ek/r2 c mc33903p mcz33903cp5ek/r2 c 5.0 v 0 3 wake-up soic 32 pin exposed pad no yes yes mcz33903cp3ek/r2 3.3 v notes 5. v dd does not allow usage of an external pnp on the 33903. output current limited to 100 ma. 6. design changes in the ?b? version resolved v sup slow ramp up issues, enhanced device curre nt consumption and improved oscillator stability. ?b? version has an errata linked to the spi operation. 7. ?c? versions are recommended for new designs . design changes in the ?c? version resolv e the spi deviation of all prior versio ns, and does not have the rxd short to ground detection feature.
analog integrated circuit device data ? freescale semiconductor 9 33903/4/5 internal block diagrams internal block diagrams figure 8. 33905 internal block diagram figure 9. 33904 internal block diagram cs sclk mosi int 5 v-can vsup1 i/o-1 miso gnd spi rst v dd regulator dbg 5v-can configurable vdd vb analog monitoring vbaux 5 v auxiliary safe signals condition & analog mux input-output v sense ve regulator v s2-int oscillator regulator state machine fail-safe power management vsup2 v s2-int vaux vcaux mux-out i/o-0 rxd txd enhanced high speed can physical interface canl canh split lin term #1 lin-t1 lin1 rxd-l1 txd-l1 lin 2.1 interface - #1 v s2-int lin term #2 lin-t2 lin2 rxd-l2 txd-l2 lin 2.1 interface - #2 v s2-int i/o-3 lin term #1 cs sclk mosi int 5 v-can vsup1 i/o-1 miso gnd spi rst v dd regulator dbg 5v-can configurable vdd vb analog monitoring vbaux 5v auxiliary safe signals condition & analog mux input-output v sense ve regulator v s2-int oscillator regulator state machine fail-safe power management vsup2 v s2-int vaux vcaux mux-out i/o-0 lin-t lin rxd-l txd-l lin 2.1 interface - #1 rxd txd enhanced high speed can physical interface canl canh split v s2-int 33905d 33905s cs sclk mosi int 5v-can vsup1 miso gnd spi rst v dd regulator dbg 5v-can configurable vdd vb analog monitoring vbaux 5v auxiliary safe signals condition & analog mux input-output vsense ve regulator v s2-int oscillator regulator state machine fail-safe power management vsup2 v s2-int vaux vcaux mux-out rxd txd enhanced high speed can physical interface canl canh split i/o-1 i/o-2 i/o-3 i/o-0
analog integrated circuit device data ? 10 freescale semiconductor 33903/4/5 internal block diagrams figure 10. 33903 internal block diagram cs sclk mosi int 5 v-can vsup2 miso gnd spi rst v dd regulator dbg 5v-can configurable vdd input-output regulator v s2-int oscillator state machine power management v s2-int i/o-0 rxd txd enhanced high speed can physical interface canl canh split safe vsup1 cs sclk mosi int 5 v-can vsup miso gnd spi rst v dd regulator dbg 5v-can configurable vdd vb analog monitoring safe signals condition & analog mux input-output v sense ve regulator v s-int oscillator state machine fail-safe power management v s-int mux-out io-0 rxd txd enhanced high-speed can physical interface canl canh split lin term #1 lin-t1 lin1 rxd-l1 txd-l1 lin 2.1 interface - #1 v s-int lin term #2 lin-t2 lin2 rxd-l2 txd-l2 lin 2.1 interface - #2 v s-int 33903 33903d i/o-3 lin term #1 cs sclk mosi int 5 v-can vsup miso gnd spi rst v dd regulator dbg 5v-can configurable vdd vb analog monitoring safe signals condition & analog mux input-output v sense ve regulator v s-int oscillator state machine fail-safe power management mux-out i/o-0 lin-t lin rxd-l txd-l lin 2.1 interface - #1 rxd txd enhanced high speed can physical interface canl canh split v s-int v s-int i/o-3 cs sclk mosi int 5 v-can vsup miso gnd spi rst v dd regulator dbg 5v-can configurable vdd vb analog monitoring safe signals condition & analog mux input-output vsense ve regulator v s-int oscillator state machine fail-safe power management mux-out i/o-0 rxd txd enhanced high speed can physical interface canl canh split v s-int i/o-2 33903s 33903p
analog integrated circuit device data ? freescale semiconductor 11 33903/4/5 pin connections pin connections figure 11. 33905d, mc33905s, mc33904 and mc33903 pin connections 4 5 6 7 8 9 10 11 12 2 3 54 51 50 49 48 47 46 45 44 43 53 52 1 13 14 15 16 42 41 40 39 mc33905d 17 18 19 20 21 22 23 24 25 26 27 38 37 36 35 34 33 32 31 30 29 28 txd-l2 gnd rxd-l2 lin-2 miso sclk mosi vsense cs vdd txd ve vb i/o-1 rxd-l1 txd-l1 lin-1 int rst rxd safe 5v-can canl split dbg canh vsup2 mux-out v-aux v-caux v-baux vsup1 lin-t1/i/o-2 gnd can lin-t2/i/o-3 i/o-0 gnd nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 4 5 6 7 8 9 10 11 12 2 3 32 29 28 27 26 25 24 23 22 21 31 30 1 13 14 15 16 20 19 18 17 mc33904 miso sclk mosi vsense cs vdd txd safe 5v-can canl split dbg canh vsup2 ve vb i/o-1 nc nc nc mux-out v-aux v-caux v-baux vsup1 i/o-2 gnd can int rst i/o-3 rxd i/o-0 4 5 6 7 8 9 10 11 12 2 3 32 29 28 27 26 25 24 23 22 21 31 30 1 13 14 15 16 20 19 18 17 mc33905s miso sclk mosi vsense cs vdd txd safe 5v-can canl split dbg canh vsup2 ve vb i/o-1 rxd-l txd-l lin mux-out v-aux v-caux v-baux vsup1 lin-t/i/o-2 gnd can int rst i/o-3 rxd i/o-0 ground ground 4 5 6 7 8 9 10 11 12 2 3 32 29 28 27 26 25 24 23 22 21 31 30 1 13 14 15 16 20 19 18 17 mc33903 miso sclk mosi cs vdd txd safe 5v-can canl split dbg canh nc nc nc nc vsup1 gnd can int rst rxd i/o-0 ground nc nc nc nc vsup2 nc nc nc nc nc note: mc33905d, mc33905s, mc33904 and mc33903 are footprint compatible, ground 32 pin exposed package gnd - lead frame 32 pin exposed package gnd - lead frame 32 pin exposed package gnd - lead frame 54 pin exposed package gnd - lead frame
analog integrated circuit device data ? 12 freescale semiconductor 33903/4/5 pin connections figure 12. 33905d, mc33905s, mc33904 and mc33903 pin connections 4 5 6 7 8 9 10 11 12 2 3 32 29 28 27 26 25 24 23 22 21 31 30 1 13 14 15 16 20 19 18 17 mc33903d miso sclk mosi vsense cs vdd txd safe 5v-can canl split dbg canh ve lin1 gnd lin2 mux-out vsup gnd can int rst rxd io-0 32 pin exposed package ground rxd-l1 txd-l1 vb lin-t2 / i/o-3 lin-t1 / i/o-2 txd-l2 gnd rxd-l2 4 5 6 7 8 9 10 11 12 2 3 32 29 28 27 26 25 24 23 22 21 31 30 1 13 14 15 16 20 19 18 17 mc33903s miso sclk mosi vsense cs vdd txd safe 5v-can canl split dbg canh ve lin gnd nc mux-out vsup gnd can int rst rxd i/o-0 32 pin exposed package ground rxd-l txd-l vb i/o-3 lin-t / i/o-2 nc gnd nc note: mc33903d, mc33903s, and mc33903p are footprint compatible. gnd - lead frame gnd - lead frame 4 5 6 7 8 9 10 11 12 2 3 32 29 28 27 26 25 24 23 22 21 31 30 1 13 14 15 16 20 19 18 17 mc33903p miso sclk mosi vsense cs vdd txd safe 5v-can canl split dbg canh ve n/c gnd nc mux-out vsup gnd can int rst rxd i/o-0 32 pin exposed package ground n/c n/c vb i/o-3 i/o-2 nc gnd nc gnd - lead frame
analog integrated circuit device data ? freescale semiconductor 13 33903/4/5 pin definitions pin definitions table 4. 33903/4/5 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 35 . 54 pin 33905d 32 pin 33905s 32 pin 33904 32 pin 33903 32 pin 33903d 32 pin 33903s 32 pin 33903p pin name pin function formal name definition 1-3, 20- 22, 27- 30, 32- 35, 52- 54 n/a 17, 18, 19 3-4,11- 14, 17- 21, 31, 32 n/a n/a n/a n/c no connect - connect to gnd. n/a n/a n/a n/a n/a 14, 16, 17 14, 16, 17, 19- 21 n/c no connect do not connect the n/c pins to gnd. leave these pins open . 4 1 1 1 2 2 2 vsup/1 power battery voltage supply 1 supply input for the device internal supplies, power on reset circuitry and the v dd regulator. vsup and vsup1 supplies are internally connected on part number mc33903bdek and mc33903bsek 5 2 2 2 n/a n/a n/a vsup2 power battery voltage supply 2 supply input for 5 v-can regulator, v aux regulator, i/o and lin pins. vsup1 and vsup2 supplies are internally connected on part number mc33903bdek and mc33903bsek 6 3 3 n/a 3 3 3 lin-t2 or i/o-3 output or input/ output lin termination 2 or input/output 3 33903d and 33905d - output pin for the lin2 master node termination resistor. or 33903p, 33903s, 33903d, 33904, 33905s and 33905d - configurable pin as an input or hs output, for connection to external circuitry (switched or small load). the input can be used as a programmable wake-up input in (lp) mode. when used as a hs, no over-temperature protection is implemented. a basic short to gnd protection function, based on switch drain-source over- voltage detection, is available. 7 4 4 n/a 4 4 4 lin-t1 or lin-t or i/o-2 output or input/ output lin termination 1 or input/output 2 33905d - output pin for the lin1 master node termination resistor. or 33903p, 33903s, 33903d, 33904, 33905s and 33905d - configurable pin as an input or hs output, for connection to external circuitry (switched or small load). the input can be used as a programmable wake-up input in (lp) mode. when used as a hs, no over-temperature protection is implemented. a basic short to gnd protection function, based on switch drain-source over- voltage detection, is available.
analog integrated circuit device data ? 14 freescale semiconductor 33903/4/5 pin definitions 8 5 5 5 5 5 5 safe output safe output (active low) output of the safe circuitry. the pin is asserted low if a fault event occurs (e.g.: software watchdog is not triggered, v dd low, issue on the rst pin, etc.). open drain structure. 9 6 6 6 6 6 6 5 v-can output 5v-can output voltage for the embedded can interface. a capacitor must be connected to this pin. 10 7 7 7 7 7 7 canh output can high can high output. 11 8 8 8 8 8 8 canl output can low can low output. 12 9 9 9 9 9 9 gnd-can ground gnd-can power gnd of the embedded can interface 13 10 10 10 10 10 10 split output split output output pin for connection to the middle point of the split can termination 14 11 11 n/a n/a n/a n/a vbaux output vb auxiliary output pin for external path pnp transistor base 15 12 12 n/a n/a n/a n/a vcaux output vcollect or auxiliary output pin for external path pnp transistor collector 16 13 13 n/a n/a n/a n/a vaux output vout auxiliary output pin for the auxiliary voltage. 17 14 14 n/a 11 11 11 mux-out output multiplex output multiplexed output to be connected to an mcu a/d input. selection of the analog parameter available at mux- out is done via the spi. a switchable internal pull-down resistor is integrated for v dd current sense measurements. 18 15 15 15 12 12 12 i/o-0 input/ output input/output 0 configurable pin as an input or output, for connection to external circuitry (switched or small load). the voltage level can be read by the spi and via the mux output pin. the input can be used as a programmable wake-up input in lp mode. in lp, when used as an output, the high side (hs) or low side (ls) can be activated for a cyclic sense function. 19 16 16 16 13 13 13 dbg input debug input to activate the debug mode. in debug mode, no watchdog refresh is necessary. outside of debug mode, connection of a resistor between dbg and gnd allows the selection of safe mode functionality. 23 n/a n/a n/a 14 n/a n/a txd-l2 input lin transmit data 2 lin bus transmit data input. includes an internal pull-up resistor to vdd. 24,31 n/a n/a n/a 15, 18 15, 18 15, 18 gnd ground ground ground of the ic. 25 n/a n/a n/a 16 n/a n/a rxd-l2 output lin receive data lin bus receive data output. table 4. 33903/4/5 pin definitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 35 . 54 pin 33905d 32 pin 33905s 32 pin 33904 32 pin 33903 32 pin 33903d 32 pin 33903s 32 pin 33903p pin name pin function formal name definition
analog integrated circuit device data ? freescale semiconductor 15 33903/4/5 pin definitions 26 n/a n/a n/a 17 n/a n/a lin2 input/ output lin bus lin bus input output connected to the lin bus. 36 17 n/a n/a 19 19 n/a 33903d/5d lin-1 33903s/5s lin input/ output lin bus lin bus input output connected to the lin bus. 37 18 n/a n/a 20 20 n/a 33903d/5d txd-l11 33903s/5s txd-l input lin transmit data lin bus transmit data input. includes an internal pull-up resistor to vdd. 38 19 n/a n/a 21 21 n/a 33903d/5d rxd-l1 33903s/5s rxd-l output lin receive data lin bus receive data output. 39 20 20 n/a 22 22 22 vsense input sense input direct battery voltage input sense. a serial resistor is required to limit the input current during high voltage transients. 40 21 21 n/a n/a n/a n/a i/o-1 input/ output input output 1 configurable pin as an input or output, for connection to external circuitry (switched or small load). the voltage level can be read by the spi and the mux output pin. the input can be used as a programmable wake-up input in (lp) mode. it can be used in association with ? i/o-0 for a cyclic sense function in (lp) mode. 41 22 22 22 23 23 23 rst output reset output (active low) this is the device reset output whose main function is to reset the mcu. this pin has an internal pull-up to vdd . the reset input voltage is also monitored in order to detect external reset and safe conditions. 42 23 23 23 24 24 24 int output interrupt output (active low) this output is asserted low when an enabled interrupt condition occurs. this pin is an open drain structure with an internal pull up resistor to vdd. 43 24 24 24 25 25 25 cs input chip select (active low) chip select pin for the spi. when the cs is low, the device is selected. in (lp) mode with v dd on, a transition on cs is a wake-up condition 44 25 25 25 26 26 26 sclk input serial data clock clock input for the serial peripheral interface (spi) of the device 45 26 26 26 27 27 27 mosi input master out / slave in spi data received by the device 46 27 27 27 28 28 28 miso output master in / slave out spi data sent to the mcu. when the cs is high, miso is high-impedance table 4. 33903/4/5 pin definitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 35 . 54 pin 33905d 32 pin 33905s 32 pin 33904 32 pin 33903 32 pin 33903d 32 pin 33903s 32 pin 33903p pin name pin function formal name definition
analog integrated circuit device data ? 16 freescale semiconductor 33903/4/5 pin definitions 47 28 28 28 29 29 29 vdd output voltage digital drain 5.0 or 3.3 v output pin of the main regulator for the microcontroller supply. 48 29 29 29 30 30 30 txd input transmit data can bus transmit data input. internal pull-up to vdd 49 30 30 30 31 31 31 rxd output receive data can bus receive data output 50 31 31 n/a 32 32 32 ve voltage emitter connection to the external pnp path transistor. this is an intermediate current supply source for the v dd regulator 51 32 32 n/a 1 1 1 vb output voltage base base output pin for connection to the external pnp pass transistor ex pad ex pad ex pad ex pad ex pad ex pad ex pad gnd ground ground ground table 4. 33903/4/5 pin definitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 35 . 54 pin 33905d 32 pin 33905s 32 pin 33904 32 pin 33903 32 pin 33903d 32 pin 33903s 32 pin 33903p pin name pin function formal name definition
analog integrated circuit device data ? freescale semiconductor 17 33903/4/5 electrical characteristics maximum ratings electrical characteristics maximum ratings table 5. maximum ratings all voltages are referenced to ground unless otherwise noted. e xceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings (8) supply voltage at vsup/1 and vsup2 normal operation (dc) transient conditions (load dump) v sup1/2 v sup1/2tr -0.3 to 28 -0.3 to 40 v dc voltage on lin/1 and lin2 normal operation (dc) transient conditions (load dump) v buslin v buslintr -28 to 28 -28 to 40 v dc voltage on canl, canh, split normal operation (dc) transient conditions (load dump) v bus v bustr -28 to 28 -32 to 40 v dc voltage at safe normal operation (dc) transient conditions (load dump) v safe v safetr -0.3 to 28 -0.3 to 40 v dc voltage at i/o-0, i/o-1, i/o-2, i/o-3 (lin-t pins) normal operation (dc) transient conditions (load dump) v i/o v i/otr -0.3 to 28 -0.3 to 40 v dc voltage on txd-l, txd-l1 txd-l2, rxd-l, rxd-l1, rxd-l2 v diglin -0.3 to v dd +0.3 v dc voltage on txd, rxd (10) v dig -0.3 to v dd +0.3 v dc voltage at int v int -0.3 to 10 v dc voltage at rst v rst -0.3 to v dd +0.3 v dc voltage at mosi, msio, sclk and cs v rst -0.3 to v dd +0.3 v dc voltage at mux-out v mux -0.3 to v dd +0.3 v dc voltage at dbg v dbg -0.3 to 10 v continuous current on canh and canl ilh 200 ma dc voltage at vdd, 5v-can, vaux, vcaux v reg -0.3 to 5.5 v dc voltage at vbase (9) and vbaux v reg -0.3 to 40 v dc voltage at ve (10) ve -0.3 to 40 v dc voltage at vsense v sense -28 to 40 v notes 8. the voltage on non-vsup pins should never exceed the v sup voltage at any time or permanent damage to the device may occur. 9. if the voltage delta between vsup/1/2 and vbase is greater than 6.0 v, the external v dd ballast current sharing functionality may be damaged. 10. potential electrical over stress (eos) damage may occur if rxd is in contact with ve while the device is on.
analog integrated circuit device data ? 18 freescale semiconductor 33903/4/5 electrical characteristics maximum ratings figure 13. pcb with top and bottom layer dissipation area (dual layer) esd capability aecq100 (11) human body model - jesd22/a114 (c zap = 100 pf, r zap = 1500 ? ) canh and canl. lin1 and lin2, pins versus all gnd pins all other pins including canh and canl charge device model - jesd22/c101 (c zap = 4.0 pf ?? corner pins (pins 1, 16, 17, and 32) all other pins (pins 2-15, 18-31) tested per iec 61000-4-2 (c zap = 150 pf, r zap = 330 ? ) device unpowered, canh and canl pi n without capacitor, versus gnd device unpowered, lin, lin1 and lin2 pin, versus gnd device unpowered, vs1/vs2 (100 nf to gnd), versus gnd tested per specific oem emc requirements for can and lin with additional capacitor on vsup/1/2 pins ( see typical applications on page 91 ) canh, canl without bus filter lin, lin1 and lin2 with and without bus filter i/o with external components (22 k - 10 nf) v esd1-1 v esd1-2 v esd2-1 v esd2-2 v esd3-1 v esd3-2 v esd3-3 v esd4-1 v esd4-2 v esd4-3 ? 8000 ? 2000 ? 750 ? 500 ? 15000 ? 15000 ? 15000 ? 9000 ? 12000 ? 7000 v thermal ratings junction temperature t j 150 c ambient temperature t a -40 to 125 c storage temperature t st -50 to 150 c thermal resistance thermal resistance junction to ambient (14) r ? ja 50 (14) c/w peak package reflow temperature during reflow (12) , (13) t pprt note 13 c notes 11. esd testing is performed in accordance with the human body model (hbm) (c zap = 100 ? pf, r zap = 1500 ? ), the charge device model (cdm), and robotic (c zap = 4.0 pf). 12. pin soldering temperature limit is for 10 seconds maximum du ration. not designed for immersion soldering. exceeding these li mits may cause malfunction or permanent damage to the device. 13. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics. 14. this parameter was measured according to figure 13 : table 5. maximum ratings (continued) all voltages are referenced to ground unless otherwise noted. e xceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit pcb 100mm x 100mm bottom side 20mm x 40mm top side, 300 sq. mm (20mmx15mm) bottom view
analog integrated circuit device data ? freescale semiconductor 19 33903/4/5 electrical characteristics static electrical characteristics static electrical characteristics table 6. static electric al characteristics characteristics noted under conditions 5.5 v ? v sup ? 28 v, - 40 ? c ? t a ? 125 ? c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit power input nominal dc voltage range (15) v sup1 /v sup2 5.5 - 28 v extended dc low voltage range (16) v sup1 /v sup2 4.0 - 5.5 v under-voltage detector thresholds, at the vsup/1 pin, low threshold (vsup/1 ramp down) ? high threshold (vsup/1 ramp up) ? hysteresis ? note: function not active in lp mode v s1_low 5.5 - 0.22 6.0 - 0.35 6.5 6.6 0.5 v under-voltage detector thresholds, at the vsup2 pin: low threshold (vsup2 ramp down) ? high threshold (vsup2 ramp up) ? hysteresis ? note: function not active in lp modes v s2_low 5.5 - 0.22 6.0 - 0.35 6.5 6.6 0.5 v v sup over-voltage detector thresholds, at the vsup/1 pin: not active in lp modes v s_high 16.5 17 18.5 v battery loss detection threshold, at the vsup/1 pin. batfail 2.0 2.8 4.0 v vsup/1 to turn v dd on, vsup/1 rising v sup-th1 - 4.1 4.5 v vsup/1 to turn v dd on, hysteresis (guaranteed by design) v sup-th1hyst 150 180 mv supply current (17) , (18) - from vsup/1 ? - from vsup2, (5v-can v aux , i/o off) i sup1 - - 2.0 0.05 4.0 0.85 ma supply current, i sup1 + i sup2 , normal mode, v dd on - 5 v-can off, v aux off ? - 5 v-can on, can interface in sleep mode, v aux off ? - 5 v-can off, vaux on ? - 5 v-can on, can interface in txd/rxd mode, v aux off, i/o-x disabled i sup1+2 - - - - 2.8 - - - 4.5 5.0 5.5 8.0 ma lp mode v dd off. wake-up from can, i/o-x inputs v sup ? ? 18 v, -40 to 25 c ? v sup ? ? 18 v, 125 c i lpm_off - - 15 - 35 50 ? a lp mode v dd on (5.0 v) with v dd under-voltage and v dd ? over-current monitoring, wake-up from can, i/o-x inputs v sup ? ? 18 v, -40 to 25 c, i dd = 1.0 ? a ? v sup ? ? 18 v, -40 to 25 c, i dd = 100 ? a ? v sup ? ? 18 v, 125 c, i dd = 100 ? a i lpm_on - - 20 40 - - 65 85 ? a lp mode, additional current for oscillator (used for: cyclic sense, forced wake- up, and in lp v dd on mode cyclic interruption and watchdog) v sup ? ? 18 v, -40 to 125 c i osc - 5.0 9.0 ? a debug mode dbg voltage range v dbg 8.0 - 10 v notes 15. all parameters in spec (ex: v dd regulator tolerance). 16. device functional, some param eters could be out of spec. v dd is active, device is not in reset mode if the lowest v dd under-voltage reset threshold is selected (approx. 3.4 v). can and i/os are not operational. 17. in run mode, can interface in sleep mode , 5 v-can and v aux turned off. i out at v dd < 50 ma. ballast: turned off or not connected. 18. vsup1 and vsup2 supplies are internally connected on part number mc33903bdek and mc33903bsek. therefore, i sup1 and i sup2 cannot be measured individually.
analog integrated circuit device data ? 20 freescale semiconductor 33903/4/5 electrical characteristics static electrical characteristics v dd voltage regulator, vdd pin output voltage v dd ? ? 5.0 v, v sup 5.5 to 28 v, i out 0 to 150 ma v dd ? ? 3.3 v, v sup 5.5 to 28 v, i out 0 to 150 ma v out -5.0 v out -3.3 4.9 3.234 5.0 3.3 5.1 3.4 v drop voltage without external pnp pass transistor (19) v dd ? ? 5.0 v, i out ? ? 100 ma v dd ? ? 5.0 v, i out ? ? 150 ma v drop - - 330 - 450 500 mv drop voltage with external transistor (19) i out ? ? 200 ma (i _ballast + i _internal ) v drop-b - 350 500 mv vsup/1 to maintain v dd within v out-3.3 specified voltage range v dd ? ? 3.3 v, i out ? ? 150 ma v dd ? ? 3.3 v, i out ? ? 200 ma, external transistor implemented v sup1-3.3 4.0 4.0 - - - - v external ballast versus internal current ratio (i _ballast = k x internal current) k 1.5 2.0 2.5 output current limitation, without external transistor i lim 150 350 550 ma temperature pre-warning (guaranteed by design) t pw - 140 - c thermal shutdown (guaranteed by design) t sd 160 - - c range of decoupling capacit or (guaranteed by design) (20) c ext 4.7 - 100 ? f lp mode v dd on, i out ? 50 ma (time limited) v dd ? ? 5.0 v, 5.6 v ?? v sup ?? 28 v v dd ? ? 3.3 v, 5.6 v ?? v sup ?? 28 v v ddlp 4.75 3.135 5.0 3.3 5.25 3.465 v lp mode v dd on, dynamic output current capabili ty (limited duration. ref. to device description). l p-ioutdc - - 50 ma lp v dd on mode: over-current wake-up threshold. hysteresis l p-ith 1.0 0.1 3.0 1.0 - - ma lp mode v dd on, drop voltage, at i out ? ? 30 ma (limited duration. ref. to device description) (19) l p-vdrop - 200 400 mv lp mode v dd on, min v sup operation (below this value, a v dd , under-voltage reset may occur) l p-minvs 5.5 - - v v dd when v sup < v sup-th1 , at i_v dd ? 10 ? a (guaranteed by design) v dd_off - - 0.3 v v dd when v sup ? v sup-th1 , at i_v dd ? 40 ma (guaranteed with parameter v sup-th1 v dd_start up 3.0 - - v notes 19. for 3.3 v v dd devices, the drop-out voltage test condition leads to a v sup below the min v sup threshold (4.0 v). as a result, the dropout voltage parameter cannot be specified. 20. the regulator is stable without an external capacitor. us age of an external capacitor is recommended for ac performance. table 6. static electrical characteristics (continued) characteristics noted under conditions 5.5 v ? v sup ? 28 v, - 40 ? c ? t a ? 125 ? c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 21 33903/4/5 electrical characteristics static electrical characteristics voltage regulator for can interface supply, 5.0 v-can pin output voltage, v sup/2 = 5.5 to 40 v i out 0 to 160 ma 5v -c out 4.75 5.0 5.25 v output current limitation (21) 5v -c ilim 160 280 - ma under-voltage threshold 5v -c uv 4.1 4.5 4.7 v thermal shutdown (guaranteed by design) 5v -cts 160 - - c external capacitance (guaranteed by design) c ext-can 1.0 - 100 ? f v auxiliary output, 5.0 and 3.3 v selectable pin vb-aux, vc-aux, vaux vaux output voltage v aux = 5.0 v, v sup = v sup2 5.5 to 40 v, i out 0 to 150 ma v aux = 3.3 v, v sup = v sup2 5.5 to 40 v, i out 0 to 150 ma v aux 4.75 3.135 5.0 3.3 5.25 3.465 v vaux under-voltage detector (vaux configured to 5.0 v) low threshold hysteresis vaux under-voltage detector (vaux configured to 3.3 v, default value) v aux-uvth 4.2 0.06 2.75 4.5 - 3.0 4.70 0.12 3.135 v vaux over-current threshold detector v aux set to 3.3 v v aux set to 5.0 v v aux-ilim 250 230 360 330 450 430 ma external capacitance (guaranteed by design) v aux cap 2.2 - 100 ? f under-voltage reset and reset function, rst pin v dd under-voltage threshold down - 90% v dd (v dd 5.0 v) (22) , (24) v dd under-voltage threshold up - 90% v dd (v dd 5.0 v) v dd under-voltage threshold down - 90% v dd (v dd 3.3 v) (22) , (24) v dd under-voltage threshold up - 90% v dd (v dd 3.3 v) v rst-th1 4.5 - 2.75 - 4.65 - 3.0 - 4.85 4.90 3.135 3.135 v v dd under-voltage reset threshold down - 70% v dd (v dd 5.0 v) (23) , (24) v rst-th2-5 2.95 3.2 3.45 v hysteresis for threshold 90% v dd , 5.0 v device for threshold 70% v dd , 5.0 v device hysteresis 3.3 v v dd for threshold 90% v dd , 3.3 v device v rst-hyst 20 10 10 - - - 150 150 150 mv v dd under-voltage reset threshold down - lp v dd on mode (note: device change to normal request mode). v dd 5.0 v (note: device change to normal request mode). v dd 3.3 v v rst-lp 4.0 2.75 4.5 3.0 4.85 3.135 v notes 21. current limitation will be reported by setting a flag. 22. generate a reset or an int . spi programmable 23. generate a reset 24. in non-lp modes table 6. static electrical characteristics (continued) characteristics noted under conditions 5.5 v ? v sup ? 28 v, - 40 ? c ? t a ? 125 ? c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? 22 freescale semiconductor 33903/4/5 electrical characteristics static electrical characteristics under-voltage reset and reset function, rst pin (continued) reset v ol @ 1.5 ma, v sup 5.5 to 28 v v ol - 300 500 mv current limitation, reset activated, v reset = 0.9 x v dd i reset low 2.5 7.0 10 ma pull-up resistor (to vdd pin) r pull-up 8.0 11 15 k ? v sup to guaranteed reset low level (25) v sup-rstl 2.5 - - v reset input threshold low threshold, v dd = 5.0 v high threshold, v dd = 5.0 v low threshold, v dd = 3.3 v high threshold, v dd = 3.3 v v rst-vth 1.5 2.5 0.99 1.65 1.9 3.0 1.17 2.0 2.2 3.5 1.32 2.31 v reset input hysteresis v hyst 0.5 1.0 1.5 v i/o pins when function selected is output i/o-0 hs switch drop @ i = -12 ma, v sup = 10.5 v v i/o-0 hsdrp - 0.5 1.4 v i/o-2 and i/o-3 hs switch drop @ i = -20 ma, v sup = 10.5 v v i/o-2-3 hsdrp - 0.5 1.4 v i/o-1, hs switch drop @ i = -400 ? a, v sup = 10.5 v v i/o-1 hsdrp - 0.4 1.4 v i/o-0, i/o-1 ls switch drop @ i = 400 ? a, v sup = 10.5 v v i/o-01 lsdrp - 0.4 1.4 v leakage current, i/o-x ? v sup i i/o_leak - 0.1 3.0 ? a i/o pins when function selected is input negative threshold v i/o_nth 1.4 2.0 2.9 v positive threshold v i/o_pth 2.1 3.0 3.8 v hysteresis v i/o_hyst 0.2 1.0 1.4 v input current, i/o ? vsup/2 i i/o_in -5.0 1.0 5.0 ? a i/o-0 and i/o-1 input resistor . i/o-0 (or i/o-1) selected in register, 2.0 v < v i/o-x <16 v (guaranteed by design). r i/o-x - 100 - k ? vsense input vsense under-voltage threshold (not active in lp modes) low threshold high threshold hysteresis v sense_th 8.1 - 0.1 8.6 - 0.25 9.0 9.1 0.5 v input resistor to gnd. in all mode s except in lp modes. (guaranteed by design). r vsense - 125 - k ? notes 25. reset must be kept low table 6. static electrical characteristics (continued) characteristics noted under conditions 5.5 v ? v sup ? 28 v, - 40 ? c ? t a ? 125 ? c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 23 33903/4/5 electrical characteristics static electrical characteristics analog mux output output voltage range, with external resistor to gnd >2.0 k ? v out_max 0.0 - v dd - 0.5 v internal pull-down resistor for regulator output current sense r mi 0.8 1.9 2.8 k ? external capacitor at mux output (26) (guaranteed by design) c mux - - 1.0 nf chip temperature sensor coeffici ent (guaranteed by design and device characterization) v dd = 5.0 v v dd = 3.3 v temp -coeff 20 13.2 21 13.9 22 14.6 mv/c chip temperature: mux-out voltage v dd = 5.0 v, t a = 125 c v dd = 3.3 v, t a = 125 c v temp 3.6 2.45 3.75 2.58 3.9 2.65 v chip temperature: mux-out voltage (guaranteed by design and characterization) t a = -40 c, v dd = 5.0 v t a = 25 c, v dd = 5.0 v t a = -40 c, v dd = 3.3 v t a = 25 c, v dd = 3.3 v v temp(gd) 0.12 1.5 0.07 1.08 0.30 1.65 0.19 1.14 0.48 1.8 0.3 1.2 v gain for v sense , with external 1.0 k 1% resistor v dd = 5.0 v v dd = 3.3 v v sense gain 5.42 8.1 5.48 8.2 5.54 8.3 offset for v sense , with external 1.0 k 1% resistor v sense offset -20 - 20 mv divider ratio for v sup/1 v dd = 5.0 v v dd = 3.3 v v sup/1 ratio 5.335 7.95 5.5 8.18 5.665 8.45 attenuation/gain ratio for i/o-0 and i/o-1 actual voltage: v dd = 5.0 v, i/o = 16 v (attenuation, mux-out register bit 3 set to 1) v dd = 5.0 v, (gain, mux-out register bit 3 set to 0) v dd = 3.3 v, i/o = 16 v (attenuation, mux-out register bit 3 set to 1) v dd = 3.3 v, (gain, mux-out register bit 3 set to 0) vi/o ratio 3.8 - 5.6 - 4.0 2.0 5.8 1.3 4.2 - 6.2 - internal reference voltage v dd = 5.0 v v dd = 3.3 v v ref 2.45 1.64 2.5 1.67 2.55 1.7 v current ratio between vdd output & i out at mux-out (i out at mux-out = i dd out / i dd_ratio ) at i out = 50 ma i _out from 25 to 150 ma i dd_ratio 80 62.5 97 97 115 117 safe output safe low level, at i = 500 ? a v ol 0.0 0.2 1.0 v safe leakage current (v dd low, or device unpowered). v safe 0 to 28 v. i safe-in - 0.0 1.0 ? a notes 26. when c is higher than cmux, a serial resistor must be inserted table 6. static electrical characteristics (continued) characteristics noted under conditions 5.5 v ? v sup ? 28 v, - 40 ? c ? t a ? 125 ? c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? 24 freescale semiconductor 33903/4/5 electrical characteristics static electrical characteristics interrupt output low voltage, i out = 1.5 ma v ol - 0.2 1.0 v pull-up resistor r pu 6.5 10 14 k ? output high level in lp v dd on mode (guaranteed by design) v oh-lpvddon 3.9 4.3 v leakage current int voltage = 10 v (to allow high-voltage on mcu int pin) v max - 35 100 ? a sink current, v int > 5.0 v, int low state i sink 2.5 6.0 10 ma miso, mosi, sclk, cs pins output low voltage, i out = 1.5 ma (miso) v ol - - 1.0 v output high voltage, i out = -0.25 ma (miso) v oh v dd -0.9 - v input low voltage (mosi, sclk, cs ) v il - - 0.3 x v dd v input high voltage (mosi, sclk, cs ) v ih 0.7 x v dd - - v tri-state leakage current (miso) i hz -2.0 - 2.0 ? a pull-up current ( cs ) i pu 200 370 500 ? a can logic input pins (txd) high level input voltage v ih 0.7 x v dd - v dd + 0.3 v low level input voltage v il -0.3 - 0.3 x v dd v pull-up current, txd, v in = 0 v v dd =5.0 v v dd =3.3 v i pdwn -850 -500 -650 -250 -200 -175 a can data output pins (rxd) low level output voltage i rxd = 5.0 ma vout low 0.0 - 0.3 x v dd v high level output voltage i rx = -3.0 ma vout high 0.7 x v dd - v dd v high level output current v rxd = v dd - 0.4 v iout high 2.5 5.0 9.0 ma low level input current v rxd = 0.4 v iout low 2.5 5.0 9.0 ma table 6. static electrical characteristics (continued) characteristics noted under conditions 5.5 v ? v sup ? 28 v, - 40 ? c ? t a ? 125 ? c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 25 33903/4/5 electrical characteristics static electrical characteristics can output pins (canh, canl) bus pins common mode voltage for full functionality v com -12 - 12 v differential input voltage threshold v canh-vcanl 500 - 900 mv differential input hysteresis v diff-hyst 50 - - mv input resistance r in 5.0 - 50 k ? differential input resistance r in-diff 10 - 100 k ? input resistance matching r in-match -3.0 0.0 3.0 % canh output voltage (45 ?? < r bus < 65 ? ? ) txd dominant state txd recessive state v canh 2.75 2.0 3.5 2.5 4.5 3.0 v canl output voltage (45 ?? < r bus < 65 ? ? ) txd dominant state txd recessive state v canl 0.5 2.0 1.5 2.5 2.25 3.0 v differential output voltage (45 ?? < r bus < 65 ? ? ) txd dominant state txd recessive state v oh -v ol 1.5 -0.5 2.0 0.0 3.0 0.05 v can h output current capability - dominant state i canh - - -30 ma can l output current capability - dominant state i canl 30 - - ma canl over-current detection - error reported in register i canl-oc 75 120 195 ma canh over-current detection - error reported in register i canh-oc -195 -120 -75 ma canh, canl input resistance to gnd, device supplied, can in sleep mode, v_canh, v_canl from 0 to 5.0 v r insleep 5.0 - 50 k ? canl, canh output voltage in lp v dd off and lp v dd on modes v canlp -0.1 0.0 0.1 v canh, canl input current, vcanh, vcanl = 0 to 5.0 v, device unpowered (vsup, vdd, 5v-can: open). (27) i can-un_sup1 - 3.0 10 a canh, canl input current, vcanh, vcanl = -2.0 to 7.0 v, device unpowered (vsup, vdd, 5v-can: open). (27) i can-un_sup2 - - 250 a differential voltage for recess ive bit detection in lp mode (28) v diff-r-lp - - 0.4 v differential voltage for dominant bit detection in lp mode (28) v diff-d-lp 1.15 - - v canh and canl diagnostic information canl to gnd detection threshold v lg 1.6 1.75 2.0 v canh to gnd detection threshold v hg 1.6 1.75 2.0 v canl to vbat detection threshold, v sup/1 and v sup2 > 8.0 v v lvb - v sup -2.0 - v canh to vbat detection threshold, v sup/1 and v sup2 > 8.0 v v hvb - v sup -2.0 - v canl to vdd detection threshold v l5 4.0 v dd -0.43 - v canh to vdd detection threshold v h5 4.0 v dd -0.43 - v notes 27. vsup, vdd, 5v-can: shorted to gnd, or connected to gnd via a 47 k resistor instances are guaranteed by design and device characterization. 28. guaranteed by design and device characterization. table 6. static electrical characteristics (continued) characteristics noted under conditions 5.5 v ? v sup ? 28 v, - 40 ? c ? t a ? 125 ? c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? 26 freescale semiconductor 33903/4/5 electrical characteristics static electrical characteristics split output voltage loaded condition i split = 500 a unloaded condition rmeasure > 1.0 m ? v split 0.3 x v dd 0.45 x v dd 0.5 x v dd 0.5 x v dd 0.7 x v dd 0.55 x v dd v leakage current -12 v < v split < +12 v -22 to -12 v < v split < +12 to +35 v i lsplit - - 0.0 - 5.0 200 a lin terminals (lin-t/1, lin-t2) lin-t1, lin-t2, hs switch drop @ i = -20 ma, v sup > 10.5 v v lt_hsdrp - 1.0 1.4 v lin1 & lin2 33903d/5d pin - lin 33903s/5s pin (parameters guaranteed for v sup/1 , v sup 2 7.0 v ?? v sup ? 18 v) operating voltage range v bat 8.0 - 18 v supply voltage range v sup 7.0 - 18 v current limitation for driver dominant state driver on, v bus = 18 v i bus_lim 40 90 200 ma input leakage current at the receiver driver off; v bus = 0 v; v bat = 12 v i bus_pas_dom -1.0 - - ma leakage output current to gnd driver off; 8.0 v ?? v bat ? 18 v; 8.0 v ?? v bus ? 18 v; v bus ? v bat i bus_pas_rec - - 20 a control unit disconnected from ground (loss of local ground must not affect communication in the residual network) ? gnd device = v sup ; v bat = 12 v; 0 < v bus < 18 v (guaranteed by design) i bus_no_gnd -1.0 - 1.0 ma v bat disconnected; v sup_device = gnd; 0 < v bus < 18 v (node has to sustain the current that can flow under this condition. bus must remain operational under this condition). (guaranteed by design) i busno_bat - - 100 a receiver dominant state v busdom - - 0.4 v sup receiver recessive state v busrec 0.6 - - v sup receiver threshold center (v th_dom + v th_rec )/2 v bus_cnt 0.475 0.5 0.525 v sup receiver threshold hysteresis (v th_rec - v th_dom ) v hys - - 0.175 v sup lin wake-up threshold from lp v dd on or lp v dd off mode v buswu - 5.3 5.8 v lin pull-up resistor to v sup r slave 20 30 60 k ? over-temperature shutdown (guaranteed by design) t linsd 140 160 180 c over-temperature shutdown hysteresis (guaranteed by design) t linsd_hys - 10 - c table 6. static electrical characteristics (continued) characteristics noted under conditions 5.5 v ? v sup ? 28 v, - 40 ? c ? t a ? 125 ? c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 27 33903/4/5 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 7. dynamic electri cal characteristics characteristics noted under conditions 5.5 v ? v sup ? 28 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit spi timing spi operation frequency (miso cap = 50 pf) freq 0.25 - 4.0 mhz sclk clock period t pclk 250 - n/a ns sclk clock high time t wsclkh 125 - n/a ns sclk clock low time t wsclkl 125 - n/a ns falling edge of cs to rising edge of sclk ?c? version ? all others t lead 30 550 - - n/a n/a ns falling edge of sclk to rising edge of cs t lag 30 - n/a ns mosi to falling edge of sclk t sisu 30 - n/a ns falling edge of sclk to mosi t sih 30 - n/a ns miso rise time (cl = 50 pf) t rso - - 30 ns miso fall time (cl = 50 pf) t fso - - 30 ns time from falling to miso low-impedance time from rising to miso high-impedance t soen t sodis - - - - 30 30 ns time from rising edge of sclk to miso data valid t valid - - 30 ns delay between falling and rising edge on cs ?c? version ? all others t cs low 1.0 5.5 - - n/a n/a ? s cs chip select low timeout detection t cs -to 2.5 - - ms supply, voltage regulator, reset v sup under-voltage detector threshold deglitcher t vs_low1/ 2_dglt 30 50 100 ? s rise time at turn on. v dd from 1.0 to 4.5 ? ? v. 2.2 ? f at the vdd pin. t rise-on 50 250 800 ? s deglitcher time to set rst pin low t rst-dglt 20 30 40 ? s reset pulse duration v dd under-voltage (spi selectable) short, default at power on when batfail bit set ? medium ? medium long ? long t rst-pulse 0.9 4.0 8.5 17 1.0 5.0 10 20 1.4 6.0 12 24 ms watchdog reset t rst-wd 0.9 1.0 1.4 ms i/o input deglitcher time (guaranteed by design) t iodt 19 30 41 ? s vsense input under-voltage deglitcher time t bft 30 - 100 ? s
analog integrated circuit device data ? 28 freescale semiconductor 33903/4/5 electrical characteristics dynamic electrical characteristics interrupt int pulse duration (refer to spi fo r selection. guaranteed by design) short (25 to 125 c) short (-40 c) ? long (25 to 125 c) long (-40 c) t int -pulse 20 20 90 90 25 25 100 100 35 40 130 140 ? s state digram timings delay for spi timer a, timer b or timer c write command after entering normal mode (no command should occur within t d_nm . t d_nm delay definition: from cs rising edge of ?go to normal mode (i.e. 0x5a00)? command to cs falling edge of ?timer write? command) t d_nm 60 - - ? s tolerance for: watchdog period in all modes, fwu delay, cyclic sense period and active time, cyclic interrupt period, lp mode over-current (unless otherwise noted) (32) t timing-acc -10 - 10 % can dynamic characteristics txd dominant state timeout t dout 300 600 1000 s bus dominant clamping detection t dom 300 600 1000 s propagation loop delay txd to rxd, recessive to dominant (fast slew rate) t lrd 60 120 210 ns propagation delay txd to can, recessive to dominant t trd - 70 110 ns propagation delay can to rxd, recessive to dominant t rrd - 45 140 ns propagation loop delay txd to rxd, do minant to recessive (fast slew rate) t ldr 100 120 200 ns propagation delay txd to can, dominant to recessive t tdr - 75 150 ns propagation delay can to rxd, dominant to recessive t rdr - 50 140 ns loop time txd to rxd, medium slew rate (selected by spi) recessive to dominant dominant to recessive t loop-msl - - 200 200 - - ns loop time txd to rxd, slow slew rate (selected by spi) recessive to dominant dominant to recessive t loop-ssl - - 300 300 - - ns can wake-up filter time, si ngle dominant pulse detection (29) (see figure 35 ) t can-wu1-f 0.5 2.0 5.0 ? s can wake-up filter time, 3 dominant pulses detection (30) t can-wu3-f 300 - - ns can wake-up filter time, 3 dom inant pulses detection timeout (31) (see figure 36 ) t can-wu3-to - - 120 ? s notes 29. no wake-up for single pulse shorter than t can-wu1 min. wake-up for single pulse longer than t can-wu1 max. 30. each pulse should be greater than t can-wu3-f min. guaranteed by design, and device characterization. 31. the 3 pulses should occur within t can-wu3-to . guaranteed by design, an d device characterization. 32. guaranteed by design. table 7. dynamic elec trical characteristics characteristics noted under conditions 5.5 v ? v sup ? 28 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless ot herwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 29 33903/4/5 electrical characteristics dynamic electrical characteristics lin physical layer: driver characteristics for normal slew rate - 20.0 kbit/sec according to lin physical layer specification bus load r bus and c bus 1.0 nf / 1.0 k ? , 6.8 nf / 660 ? , 10 nf / 500 ? . see figure 18 , page 32 . duty cycle 1: th rec(max) = 0.744 * v sup th dom(max) = 0.581 * v sup d1 = t bus_rec(min) /(2 x t bit ), t bit = 50 s, 7.0 v ?? v sup ??? 18 v d1 0.396 - - duty cycle 2: th rec(min) = 0.422 * v sup th dom(min) = 0.284 * v sup d2 = t bus_rec(max) /(2 x t bit ), t bit = 50 s, 7.6 v ?? v sup ??? 18 v d2 - - 0.581 lin physical layer: driver characteristics for slow slew rate - 10.4 kbit/sec according to lin physical layer specification bus load r bus and c bus 1.0 nf / 1.0 k ? , 6.8 nf / 660 ? , 10 nf / 500 ? . measurement thresholds. see figure 19 , page 33 . duty cycle 3: th rec(max) = 0.778 * v sup th dom(max) = 0.616 * v sup d3 = t bus_rec(min) /(2 x t bit ), t bit = 96 s, 7.0 v ?? v sup ??? 18 v d3 0.417 - - duty cycle 4: th rec(min) = 0.389 * v sup th dom(min) = 0.251 * v sup d4 = t bus_rec(max) /(2 x t bit ), t bit = 96 s, 7.6 v ?? v sup ??? 18 v d4 - - 0.590 lin physical layer: driver characteristics for fast slew rate lin fast slew rate (programming mode) sr fast - 20 - v / ? s lin physical layer: characteristics and wake-up timings v sup from 7.0 to 18 v, bus load r bus and c bus 1.0 nf / 1.0 k ? , 6.8 nf / 660 ? , 10 nf / 500 ? . see figure 18 , page 32 . propagation delay and symmetry (see figure 18 , page 31 and figure 19 , page 33 ) propagation delay of receiver, t rec_pd = max (t rec_pdr , t rec_pdf ) symmetry of receiver propagation delay, t rec_pdf - t rec_pdr t rec_pd t rec_sym - - 2.0 4.2 - 6.0 2.0 ? s bus wake-up deglitcher (lp v dd off and lp v dd on modes) (see figure 20 , page 32 for lp v dd off mode and figure 21 , page 33 for lp mode) t propwl 42 70 95 ? s bus wake-up event reported from lp v dd off mode from lp v dd on mode t wake_lpvdd off t wake_lpvdd on - 1.0 - - 1500 12 ? s txd permanent dominant state delay (guaranteed by design) t txddom 0.65 1.0 1.35 s table 7. dynamic elec trical characteristics characteristics noted under conditions 5.5 v ? v sup ? 28 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless ot herwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? 30 freescale semiconductor 33903/4/5 electrical characteristics timing diagrams timing diagrams figure 14. spi timings figure 15. can signal propagation loop delay txd to rxd di 0 do 0 undefined don?t care di n don?t care t lead t sih t sisu t lag t pclk t wclkh t wclkl t valid do n t sodis cs sclk mosi miso t soen t cs low txd rxd 0.3 x v dd t lrd 0.7 x v dd t ldr 0.3 x v dd 0.7 x v dd
analog integrated circuit device data ? freescale semiconductor 31 33903/4/5 electrical characteristics timing diagrams figure 16. can signal propagation delays txd to can and can to rxd . figure 17. test circuit for can timing characteristics txd v diff 0.9 v t trd 0.5 v t tdr rxd t rrd t rdr 0.3 x vdd 0.7 x v dd 0.3 x v dd 0.7 x v dd vsup 12 v canl 22 ? f 10 ? f split gnd txd rxd signal generator all pins are not shown r bus 15 pf c bus 100 pf 60 ? 100 nf 5 v_can canh
analog integrated circuit device data ? 32 freescale semiconductor 33903/4/5 electrical characteristics timing diagrams figure 18. lin timing measu rements for normal slew rate txd lin rxd t bit t bit t bus_dom (max) t bus_rec (min) t rec_pdf(1) 74.4% v sup 42.2% v sup 58.1% v sup 28.4% v sup t bus_rec (max) v lin_rec t bus_dom (min) rxd output of receiving node 1 output of receiving node 2 th rec(max) th dom(max) th rec(min) th dom(min) thresholds of receiving node 1 thresholds of receiving node 2 t rec_pdr(1) t rec_pdf(2) t rec_pdr(2)
analog integrated circuit device data ? freescale semiconductor 33 33903/4/5 electrical characteristics timing diagrams figure 19. lin timing measurements for slow slew rate figure 20. lin wake-up lp v dd off mode timing txd lin rxd t bit t bit t bus_dom (max) t bus_rec (min) t rec_pdf(1) 77.8% v sup 38.9% v sup 61.6% v sup 25.1% v sup t bus_rec (max) v lin_rec t bus_dom (min) rxd output of receiving node 1 output of receiving node 2 th rec(max) th dom(max) th rec(min) th dom(min) thresholds of receiving node 1 thresholds of receiving node 2 t rec_pdr(1) t rec_pdf(2) t rec_pdr(2) vdd lin v tt dominant level 0.4 v v 3v sup propwl wake buswu rec
analog integrated circuit device data ? 34 freescale semiconductor 33903/4/5 electrical characteristics timing diagrams figure 21. lin wake-up lp v dd on mode timing irq lin v lin_rec tt dominant level 0.4 v v irq stays low until spi reading command propwl wake buswu sup
analog integrated circuit device data ? freescale semiconductor 35 33903/4/5 functional description introduction functional description introduction the mc33903_4_5 is the second generation of system basis chip, combining: - advanced power management unit for the mcu, the integrated can interface and for the additional ics such as sensors, can transceiver. - built in enhanced high speed can interface (iso11898- 2 and -5), with local and bus fa ilure diagnostic, protection, and fail-safe operation mode. - built in lin interface, compliant to lin 2.1 and j2602-2 specification, with local and bus failure diagnostic and protection. - innovative hardware configurable fail-safe state machine solution. - multiple lp modes, with low current consumption. - family concept with pin co mpatibility; with and without lin interface devices. functional pin description power supply (vsup/1 and vsup2) note: vsup1 and vsup2 supplies are externally available on all devices except the 33903d, 33903s, and 33903p, where these are connected internally. vsup1 is the input pin for the internal supply and the vdd regulator. vsup2 is the input pin for the 5 v-can regulator, lin?s interfaces and i/o functions. the vsup block includes over and under-voltage detec tions which can generate interrupt. the device includes a loss of battery detector connected to vsup/1. loss of battery is reported through a bit (called batfail). this generates a por (power on reset). vdd voltage regulator (vdd) the regulator has two main modes of operation (normal mode and lp mode). it can operate with or without an external pnp transistor. in normal mode, without external pnp, the max dc capability is 150 ma. current limitation, temperature pre- warning flag and over-temperature shutdown features are included. when v dd is turned on, rise time from 0 to 5.0 v is controlled. output voltage is 5.0 v. a 3.3 v option is available via dedicated part number. if current higher than 150 ma is required, an external pnp transistor must be connected to ve (pnp emitter) and vb (pnp base) pins, in order to increase total current capability and share the power dissipation between internal vdd transistor and the external transistor. see external transistor q1 (ve and vb) . the pnp can be used even if current is less than 150 ma, depending upon ambient temperature, maximum supply and thermal resistance. typically, above 100-200 ma, an external ballast transistor is recommended. vdd regulator in lp mode when the device is set in lp v dd on mode, the v dd regulator is able to supply the mcu with a dc current below typically 1.5 ma ( l p-ith ). transient current can also be supplied up to a tenth of a ma. current in excess of 1.5 ma is detected, and this event is managed by the device logic (wake-up detection, timer start for over-current duration monitoring or watchdog refresh). external transistor q1 (ve and vb) the device has a dedicated circuit to allow usage of an external ?p? type transistor, with the objective to share the power dissipation between the internal transistor of the v dd regulator and the external transistor. the recommended bipolar pnp transistor is mjd42c or bcp52-16. when the external pnp is connected, the current is shared between the internal path transistor and the external pnp, with the following typical ratio: 1/3 in the internal transistor and 2/3 in the external pnp. the pnp activation and control is done by spi. the device is able to oper ate without an external transistor. in this case, the ve and vb pins must remain open. 5 v-can voltage regulator for can and analog mux this regulator is supplied from the vsup/2 pin. a capacitor is required at 5 v-can pin. analog mux and part of the lin interfaces are supplied from 5 v-can. consequently, the 5 v-can must be on in order to have analog mux operating and to have the lin interface operating in txd/rxd mode. the 5 v-can regulator is off by default and must be turned on by spi. in debug mode, the 5 v-can is on by default. v auxiliary output, 5.0 and 3.3 v selectable (vb-aux, vc-aux, and vcaux) - q2 the vaux block is used to provide an auxiliary voltage output, 5.0 or 3.3 v, selectable by the spi. it uses an external pnp pass transistor for flexibility and power dissipation constraints. the external recommended bipolar transistors are mjd42c or bcp52-16. an over-current and under-voltage detectors are provided.
analog integrated circuit device data ? 36 freescale semiconductor 33903/4/5 functional description functional pin description v aux is controlled via the spi, and can be turned on or off. v aux low threshold detection and over-current information will disable v aux , and are reported in the spi and can generate int . v aux is off by default and must be turned on by the spi. under-voltage reset and reset function ( rst ) the rst pin is an open drain structure with an internal pull-up resistor. the ls driver has limited current capability when asserted low, in order to tolerate a short to 5.0 v. the rst pin voltage is monitored in order to detect failure (e.g. rst pin shorted to 5.0 v or gnd). the rst pin reports an under-voltage condition to the mcu at the vdd pin, as a rst failure in the watchdog refresh operation. v dd under-voltage reset also operates in lp v dd on mode. two v dd under-voltage thresholds are included. the upper (typically 4.65 v, r st-th1-5 ) can lead to a reset or an interrupt. this is selected by the spi. when ?r st-th2-5 ?is selected, in normal mode, an int is asserted when vdd falls below ?r st-th1-5 ?, then, when v dd falls below ?r st-th2-5 ? a reset will occur. this will allow the mcu to operate in a degraded mode (i.e., with 4.0 v v dd ). i/o pins (i/o-0: i/o-3) i/os are configurable input/output pins. they can be used for small loads or to drive exte rnal transistors. when used as output drivers, the i/os are eith er a hs or ls type. they can also be set to high-impedance. i/os are controlled by the spi and at power on, the i/os are set as inputs. they include over-load protection by temper ature or excess of a voltage drop. when i/o-0/-1/-2/-3 voltage is greater than vsup/2 voltage, the leakage current ( i i/o_leak ) parameter is not applicable ? i/o-0 and i/o-1 will have current flowing into the device through three diodes limited by an 80 kohm resistor (in series). ? i/o-2 and i/o-3 will have unlimited current flowing into the device through one diode. in lp mode, the state of the i/o can be turned on or off, with extremely low power consum ption (except when there is a load). protection is disabled in lp mode. when cyclic sense is used, i/o-0 is the hs/ls switch, i/o- 1, -2 and -3 are the wake inputs. i/o-2 and i/o-3 pins share the lin master pin function. vsense input (vsense) this pin can be connected to the battery line (before the reverse battery protection diode), via a serial resistor and a capacitor to gnd. it incorporates a threshold detector to sense the battery voltage a nd provide a battery early warning. it also includes a resistor divider to measure the v sense voltage via the mux-out pin. mux-output (muxout) the mux-out pin ( figure 22 ) delivers an analog voltage to the mcu a/d input. the voltage to be delivered to mux- out is selected via the spi, from one of the following functions: v sup/1 , v sense , i/o-0, i/o-1, internal 2.5 v reference, die temperature sensor, v dd current copy. voltage divider or amplifier is inserted in the chain, as shown in figure 22 . for the v dd current copy, a resistor must be added to the mux-out pin, to convert curre nt into voltage. device includes an internal 2.0 k resistor selectable by the spi. voltage range at mux-out is from gnd to vdd. it is automatically limited to v dd (max 3.3 v for 3.3 v part numbers). the mux-out buffer is supplied from 5 v-can regulator, so the 5 v-can regulator must be on in order to have: 1) mux-out functionality and 2) spi selection of the analog function. if the 5 v-can is off, the mux-out voltage is near gnd and the spi command that selects one of the analog inputs is ignored. delay must be respected between spi commands for 5 v- can turned on and spi to select mux-out function. the delay depends mainly upon the 5 v-can capacitor and load on 5 v-can. the delay can be estimated using the following formula: delay = c(5 v-can) x u (5.0 v) / i_lim 5 v-can. c = cap at 5 v-can regulator, u = 5.0 v, i _lim 5 v-can = min current limit of 5 v-can regulator (parameter 5 v -c ilim ).
analog integrated circuit device data ? freescale semiconductor 37 33903/4/5 functional description functional pin description figure 22. analog multiplexer block diagram dgb (dgb) and debug mode primary function it is an input used to set the device in debug mode. this is achieved by applying a voltage between 8.0 and 10 v at the debug pin and then, powering up the device (see state diagram ). when the device leaves the init reset mode and enters into init mode, it detects the voltage at the debug pin to be between a range of 8.0 to 10 v, and activates the debug mode. when debug mode is detected, no watchdog spi refresh commands are necessary. this allows an easy debug of the hardware and software routines (i.e. spi commands). when the device is in debug mode it is reported by the spi flag. while in debug mode, and the voltage at dbg pin falls below the 8.0 to 10 v range, the debug mode is left, and the device starts the watchdog oper ation, and expects the proper watchdog refresh. the debug mode can be left by spi. this is recommended to avoid staying in debug mode when an unwanted debug mode selection (fmea pin) is present. the spi command has a higher priority than providing 8.0 to 10 v at the debug pin. secondary function the resistor connected between the dbg pin and the gnd selects the fail-safe mode operation. dbg pin can also be connected directly to gnd (thi s prevents the usage of debug mode). flexibility is provided to select safe output operation via a resistor at the dbg pin or via a spi command. the spi command has higher priority than the hardware selection via debug resistor. when the debug mode is selected, the safe modes cannot be configured via the re sistor connected at dbg pin. safe safe output pin this pin is an output and is asse rted low when a fault event occurs. the objective is to drive electrical safe circuitry and set the ecu in a known state, independent of the mcu and sbc, once a failure has been detected. the safe output structure is an open drain, without a pull- up. interrupt ( int ) the int output pin is asserted low or generates a low pulse when an interrupt condition occurs. the int condition is enabled in the int register. the selection of low level or pulse and pulse duration are selected by spi. no current will flow inside the int structure when v dd is low, and the device is in lp v dd off mode. this allows the connection of an external pull-up resistor and connection of an int pin from other ics without extra consumption in unpowered mode. d1 v bat vsup/1 s_in i/o-1 i/o-0 m ultiplexer v dd-i_copy r m(*) (*)optional a/d in mcu s_iddc mux-out s_g3.3 te m p vsense s_g5 r sense 1.0 k r mi s_ir s_in s_in s_in v ref : 2.5 v 5v-can s_i/o_att s_i/o_att all swicthes and resistor are configured and controlled via the spi r m : internal resistor connected when v reg current monitor is used s_g3.3 and s_g5 for 5.0 v or 3.3 v vdd versions s_iddc to select v dd regulator current copy s_in1 for lp mode resistor bridge disconnection s_ir to switch on/off of the internal r mi resistor s_i/o_att for i/o-0 and i/o-1 attenuation selection buffer 5v-can
analog integrated circuit device data ? 38 freescale semiconductor 33903/4/5 functional description functional pin description int has an internal pull-up structure to v dd . in lp v dd on mode, a diode is inserted in series with the pull-up, so the high level is slightly lower than in other modes. canh, canl, split, rxd, txd these are the pins of the high speed can physical interface, between the can bus and the micro controller. a detail description is provided in the document. lin, lin-t, txdl and rxdl these are the pins of the lin physical interface. device contains zero, one or two lin interfaces. the mc33903, mc33903p, and mc33904 do not have a lin interface. however, the mc33903s/5s (s = single) and mc33903d/5d (d=dual) contain 1 and 2 lin interfaces, respectively. lin, lin1 and lin2 pins are the connection to the lin sub buses. lin interfaces are connecte d to the mcu via the txd, txd-l1 and txd-l2 and rxd, rxd-l1 and rxd-l2 pins. the device also includes one or two hs switches to vsup/ 2 pin which can be used as a lin master termination switch. pins lint, lint-1 and lint-2 pins are the same as ? i/o-2 and i/o-3.
analog integrated circuit device data ? freescale semiconductor 39 33903/4/5 functional device operation mode and state description functional device operation mode and state description the device has several operation modes. the transitions and conditions to enter or leav e each mode are illustrated in the state diagram . init reset this mode is automatically entered after the device is ?powered on?. in this mode, the rst pin is asserted low, for a duration of typically 1.0 ms. control bits and flags are ?set? to their default reset condition. the batfail is set to indicate the device is coming from an unpowered condition, and all previous device configurations are lost and ?reset? the default value. the duration of the init reset is typically 1.0 ms. init reset mode is also entered from init mode if the expected spi command does not occur in due time (ref. init mode), and if the device is not in the debug mode. init this mode is automatically entered from the init reset mode. in this mode, the devic e must be configured via spi within a time of 256 ms max. four registers called init wdog, init reg, init lin i/o and init misc must be, and can only be configured during init mode. other registers can be written in this and other modes. once the init register c onfiguration is done, a spi watchdog refresh command must be sent in order to set the device into normal mode. if the spi watchdog refresh does not occur within the 256 ms period, the device will return into init reset mode for typically 1.0 ms, and then re enter into init mode. register read operation is allowed in init mode to collect device status or to read back th e init register configuration. when init mode is left by a spi watchdog refresh command, it is only possible to re-enter the init mode using a secured spi command. in init mode, the can, lin1, lin2, vaux, i/o_x and analog mux functions are not operating. the 5 v-can is also not operating, except if the debug mode is detected. reset in this mode, the rst pin is asserted low. reset mode is entered from normal mode, normal request mode, lp v dd on mode and from the flash mode when the watchdog is not triggered, or if a v dd low condition is detected. the duration of reset is typically 1.0 ms by default. you can define a longer reset pulse activation only when the reset mode is entered following a v dd low condition. reset pulse is always 1.0 ms, when reset mode is entered due to wrong watchdog refresh command. reset mode can be entered via the secured spi command. normal request this mode is automatically entered after reset mode, or after a wake-up from lp v dd on mode. a watchdog refresh spi command is necessary to transition to normal mode. the duration of the normal request mode is 256 ms when normal request mode is entered after reset mode. different durations can be selected by spi when normal request is entered from lp v dd on mode. if the watchdog refresh spi command does not occur within the 256 ms (or the shorter user defined time out), then the device will enter into reset mode for a duration of typically 1.0 ms. note: in init reset, init, reset and normal request modes as well as in lp modes, the v dd external pnp is disabled. normal in this mode, all device functions are available. this mode is entered by a spi watchdog refresh command from normal request mode, or from init mode. during normal mode, the device watchdog function is operating, and a periodic watchdog refresh must occur. when an incorrect or missing watchdog refresh command is initiated, the device will enter into reset mode. while in normal mode, the device can be set to lp modes (lp v dd on or lp v dd off) using the spi command. dedicated, secured spi comma nds must be used to enter from normal mode to reset mode, init mode or flash mode. flash in this mode, the software watchdog period is extended up to typically 32 seconds. this allow programming of the mcu flash memory while minimizing the software over head to refresh the watchdog. the flas h mode is entered by secured spi command and is left by spi command. device will enter into reset mode. when an incorrect or missing watchdog refresh command device will enter into reset mode. an interrupt can be generated at 50% of the watchdog period. can interface operates in flash mode to allow flash via can bus, inside the vehicle. debug debug is a special operation mode of the device which allows for easy software and hardware debugging. the debug operation is detected after power up if the dbg pin is set to 8.0 to 10 v range. when debug is detected, all the software watchdog operations are disabled: 256 ms of init mode, watchdog refresh of normal mode and flash mode, normal request time out (256 ms or user defined val ue) are not operating and will not lead to transition into init reset or reset mode. when the device is in debug mode, the spi command can be sent without any time constraints with respect to the watchdog operation and the mcu program can be ?halted? or ?paused? to verify proper operation.
analog integrated circuit device data ? 40 freescale semiconductor 33903/4/5 functional device operation lp modes debug can be left by removing 8 to 10 v from the debug pin, or by the spi comma nd (ref. to mode register). the 5 v-can regulator is on by default in debug mode. lp modes the device has two main lp modes: lp mode with v dd off, and lp mode with v dd on. prior to entering into lp mode, i/o and can wake-up flags must be cleared (ref. to mode register). if the wake-up flags are not cleared, the device will not enter into lp mode. in addition, the can failure flags (i.e. can_f and can_uf) must be cleared, in order to meet the lp current consumption specification. lp - v dd off in this mode, v dd is turned off and the mcu connected to vdd is unsupplied. this mode is entered using spi. it can also be entered by an automatic transition due to fail-safe management. 5 v-can and v aux regulators are also turned off. when the device is in lp v dd off mode, it monitors external events to wake-up and leave the lp mode. the wake-up events can occur from: ?can ? lin interface, depending upon device part number ? expiration of an internal timer ? i/o-0, and i/o-1 inputs, and depending upon device part number and configuration, i/o-2 and/or -3 input ? cyclic sense of i/o-1 input, associated by i/o-0 activation, and depending upon device part number and configuration, cyclic sense of i/o-2 and -3 input, associated by i/o-0 activation when a wake-up event is detec ted, the device enters into reset mode and then into normal request mode. the wake- up sources are reported to the device spi registers. in summary, a wake-up event from lp v dd off leads to the v dd regulator turned on, and the mcu operation restart. lp - v dd on in this mode, the voltage at the vdd pin remains at 5.0 v (or 3.3 v, depending upon device part number). the objective is to maintain the mcu powered, with reduced consumption. in such mode, the dc output current is expected to be limited to 100 ? a or a few ma, as the ecu is in reduced power operation mode. during this mode, the 5 v-can and v aux regulators are off. the optional external pnp at vdd will also be automatically disabled when entering this mode. the same wake-up events as in lp v dd off mode (can, lin, i/o, timer, cyclic sense) are available in lp v dd on mode. in addition, two additional wake-up conditions are available. ? dedicated spi command. when device is in lp v dd on mode, the wake-up by spi command uses a write to ?normal request mode?, 0x5c10. ? output current from vdd exceeding l p-ith threshold. in lp v dd on mode, the device is able to source several tenths of ma dc. the current s ource capability can be time limited, by a selectable internal timer. timer duration is up to 32 ms, and is triggered when th e output current exceed the output current threshold typically 1.5 ma. this allows for instance, a periodic activation of the mcu, while the device remains in lp v dd on mode. if the duration exceed the selected time (ex 32 ms), the device will detect a wake-up. wake-up events are reported to the mcu via a low level pulse at int pulse. the mcu will detect the int pulse and resume operation. watchdog function in lp v dd on mode it is possible to enable the watchdog function in lp v dd on mode. in this case, the principle is timeout. refresh of the watchdog is done either by: ? a dedicated spi command (different from any other spi command or simple cs activation which would wake- up - ref. to the previous paragraph) ? or by a temporary (less than 32 ms max) v dd over current wake-up (i dd > 1.5 ma typically). as long as the watchdog refresh occurs, the device remains in lp v dd on mode. mode transitions mode transitions are either do ne automatically (i.e. after a timeout expired or voltage conditi ons), or via a spi command, or by an external event such as a wake-up. some mode changes are performed using the secured spi commands.
analog integrated circuit device data ? freescale semiconductor 41 33903/4/5 functional device operation state diagram state diagram figure 23. state diagram init reset start t_ ir init start t_ init t_ ir expired t_ init expired or v dd v sup-th1 normal start t_ nr request (256 ms or config) (1) watchdog refresh in closed window or enhanced watchdog refresh failure t_ r expired spi write (0x5a00) t_ nr expired lp start t_ wdl (2) v dd on lp v dd off wake-up if enable wake-up (5) (2) if enable by spi, prior to enter lp v dd on mode lp v dd on start t_ oc time i dd > 1.5 ma i- dd >i oc i- dd v dd _ uvth watchdog refresh spi or t_ wdf expired or v dd v dd_uvth ext reset (3) ref. to ?spi secure? description (4) v dd external pnp is disable in all mode except normal and flash modes. (5) wake-up from lp v dd on mode by spi command is done by a spi mode change: 0x5c10 or vdd t sd
analog integrated circuit device data ? 42 freescale semiconductor 33903/4/5 functional device operation mode change mode change ?secured spi? description: a request is done by a spi command, the device provide on miso an unpredictable ?random code?. software must perform a logical change on the code and return it to the device with the new spi command to perform the desired action. the ?random code? is different at every exercise of the secured procedure and can be read back at any time. the secured spi uses the special mode register for the following transitions: - from normal mode to int mode - from normal mode to flash mode - from normal mode to reset mode (reset request). ?random code? is also used when the ?advance watchdog? is selected. changing of device critical parameters some critical parameters are configured one time at device power on only, while the batfail flag is set in the init mode. if a change is required while device is no longer in init mode, device must be set back in init mode using the ?spi secure? procedure. watchdog operation in normal request mode in normal request mode, the device expects to receive a watchdog configuration before the end of the normal request time out period. this period is reset to a long (256 ms) after power on and when batfail is set. the device can be configured to a different (shorter) time out period which can be used after wake-up from lp v dd on mode. after a software watchdog rese t, the value is restored to 256 ms, in order to allow for a comp lete software initialization, similar to a device power up. in normal request mode the watchdog operation is ?timeout? only and can be trig gered/observed any time within the period. watchdog type selection three types of watchdog operation can be used: - window watchdog (default) - timeout operation - advanced the selection of watchdog is performed in init mode. this is done after device power up and when the batfail flag is set. the watchdog configuration is done via the spi, then the watchdog mode selection content is locked and can be changed only via a secured spi procedure. window watchdog operation the window watchdog is available in normal mode only. the watchdog period selection can be kept (spi is selectable in init mode), while the device enters into lp v dd on mode. the watchdog period is reset to the default long period after batfail. the period and the refresh of watchdog are done by the spi. a refresh must be done in the open window of the period, which starts at 50% of the selected period and ends at the end of the period. if the watchdog is triggered be fore 50%, or not triggered before end of period, a reset has occurred. the device enters into reset mode. watchdog in debug mode when the device is in debug mode (entered via the dbg pin), the watchdog continues to operate but does not affect the device operation by asserting a reset. for the user, operation appears wit hout the watchdog. when debug mode is set by software (spi mode reg), the watchdog period starts at the end of the spi command. when debug mode is set by hardware (dbg pin below 8- 10 v), the device enters into reset mode. watchdog in flash mode during flash mode, watchdog can be set to a long timeout period. watchdog is timeout only and an int pulse can be generated at 50% of the time window. advance watchdog operation when the advance watchdog is selected (at init mode), the refresh of the watchdog must be done using a random number and with 1, 2, or 4 spi commands. the number for the spi command is sele cted in init mode. the software must read a random byte from the device, and then must return the random byte inverted to clear the watchdog. the random byte write can be performed in 1, 2, or 4 different spi commands. if one command is selected, a ll eight bits are written at once. if two commands are selected, the first write command must include four of the eight bits of the inverted random byte. the second command must include the next four bits. this completes the watchdog refresh. if four commands are select ed, the first write command must include two of the eight bits of the inverted random byte. the second command must include the next two bits, the 3rd command must include the next two, and the last command,
analog integrated circuit device data ? freescale semiconductor 43 33903/4/5 functional device operation watchdog operation must include the last two. this completes the watchdog refresh. when multiple writes are used, the most significant bits are sent first. the latest spi command needs to be done inside the open window time frame, if window watchdog is selected. detail spi operation and spi commands for all watchdog types. all spi commands and examples do not use parity functions. in init mode, the watchdog type (window, timeout, advance and number of spi co mmands) is selected using the register init watchdog, bits 1, 2 and 3. the watchdog period is selected using the tim_a register. the watchdog period selection can also be done in normal mode or in normal request mode. transition from init mode to normal mode or from normal request mode to normal mode is done using a single watchdog refresh command (spi 0x 5a00). while in normal mode, the watchdog refresh command depends upon the watchdog type selected in init mode. they are detailed in the paragraph below: simple watchdog the refresh command is 0x5a 00. it can be send any time within the watchdog period, if the timeout watchdog operation is selected (init-watchdog register, bit 1 wd n/win = 0). it must be send in the open window (second half of the period) if the window watchdog operation was selected (init- watchdog register, bit 1 wd n/win = 1). advance watchdog the first time the device enters into normal mode (entry on normal mode using the 0x5a00 command), random (rndm) code must be read using the spi command, 0x1b00. the device returns on miso second byte the rndm code. the full 16 bits miso is called 0x xxrd. rd is the complement of the rd byte. advance watchdog, refresh by 1 spi command the refresh command is 0x5a rd. during each refresh command, the device will return on miso, a new random code. this new random code must be inverted and send along with the next refresh comm and. it must be done in an open window, if the window operation was selected. advance watchdog, refresh by two spi commands: the refresh command is split in two spi commands. the first partial refresh command is 0x5aw1, and the second is 0x5aw2. byte w1 cont ains the first four inverted bits of the rd byte plus the last four bits equal to zero. byte w2 contains four bits equal to zero plus the last four inverted bits of the rd byte. during this second refresh command the device returns on miso a new random code. this new random code must be inverted and send along with the next two refresh commands and so on. the second command must be done in an open window if the window operation was selected. advance watchdog, refresh by four spi commands the refresh command is split into four spi commands. the first partial refresh command is 0x5aw1, the second is 0x5aw2, the third is 0x5aw3, and the last is 0x5aw4. byte w1 contains the first two inverted bits of the rd byte, plus the last six bits equal to zero. byte w2 contains two bits equal to zero, plus the next two inverted bits of the rd byte, plus four bits equal to zero. byte w3 contains four bits equal to zero, plus the next two inverted bits of the rd byte, plus two bits equal to zero. byte w4 contains six bits equal to zero, plus the next two inverted bits of the rd byte. during this fourth refresh command, the device will return, on miso, a new random code. this new random code must be inverted and send along with the next four refresh commands. the fourth command must be done in an open window if the window operation was selected. proper response to int during a device detect upon an int , the software handles the int in a timely manner: access of the int register is done within two watchdog periods. this feature must be enabled by spi using the init watchdog register bit 7.
analog integrated circuit device data ? 44 freescale semiconductor 33903/4/5 functional device operation functional block operation versus mode functional block operation versus mode the 5 v-can default is on when the device is powered-up and se t in debug mode. it is fully controllable via the spi command. table 8. device block operation for each state state v dd 5 v-can i/o-x v aux can lin1/2 power down off off off off high-impedance high-impedance init reset on off hs/ls off wake-up disable off off: can termination 25 k to gnd transmitter / receiver /wake-up off off: internal 30 k pull-up active. transmitter: receiver / wake-up off. lin term off init on off (34) wu disable (35) (36) (37) off off off reset on keep spi config wu disable (35) (36) (37) off off off normal request on keep spi config wu disable (35) (36) (37) off off off normal on spi config spi config wu spi config spi config spi config spi config lp v dd off off off user defined wu spi config off off + wake-up en/dis off + wake-up en/dis lp v dd on on (33) off user defined wu spi config off off + wake-up en/dis off + wake-up en/dis safe output low: safe case a safe case a:on safe case b: off a: keep spi config, b: off hs/ls off wake-up by change state off off + wake-up enable off + wake-up enable flash on spi config spi config off spi config off notes 33. with limited current capability 34. 5 v-can is on in debug mode. 35. i/o-0 and i/o-1, configured as an output high-side switch and on in normal mode will remain on in reset, init or normal request. 36. i/o-0, configured as an output low-side switch and on in normal mode will turn off when entering reset mode, resume operation in normal mode. 37. i/o-1, configured as an output low-side switch and on in no rmal mode will remain on in reset, init or normal request.
analog integrated circuit device data ? freescale semiconductor 45 33903/4/5 functional device operation illustration of device mode transitions. illustration of devi ce mode transitions. figure 24. power up normal and lp modes v sup v dd rst int spi mode v dd-uv (4.5 v typically) reset init series of spi single spi normal batfail 5v-can >4.0 v vaux a power up to normal mode b s_11 s_1 s_11: write int registers s_1: go to normal mode s_12 s_2 v dd-uv normal lp v dd off c s_2: go to lp v dd off mode s_12: lp mode configuration b normal to lp v sup v dd rst int spi 5v-can vaux legend: s_13 s_3 normal lp v dd on d b normal to lp v sup v dd rst int spi 5v-can vaux s_13: lp mode configuration s_3: go to lp mode v dd off mode v dd on mode
analog integrated circuit device data ? 46 freescale semiconductor 33903/4/5 functional device operation illustration of device mode transitions. figure 25. wake-up from lp modes c wake-up from lp v dd off mode v dd -uv (4.5 v typically) reset normal s_14 s_4 request normal can bus based on reg configuration based on reg configuration can wake-up i/o-x toggle pattern available wake- up events (exclusive) wake-up detected start fwu timer duration (50-8192 ms) . spi selectable fwu timer lp v dd _off v sup v dd rst int spi mode 5v-can vaux d s_14 s_4 normal request normal lp v dd on based on reg configuration based on reg configuration can bus can wake-up i/o-x toggle pattern i dd current i dd-oc (3.0 ma typically) i dd oc deglitcher or timer (100 us typically, 3 -32 ms) wake-up detected start fwu timer duration (50-8192 ms) stop spi selectable fwu timer spi wake-up from lp v dd on mode v sup v dd rst int spi mode 5v-can vaux lin bus lin wake-up filter lin bus lin wake-up filter
analog integrated circuit device data ? freescale semiconductor 47 33903/4/5 functional device operation cyclic sense operation during lp modes cyclic sense operation during lp modes this function can be used in both lp modes: v dd off and v dd on. cyclic sense is the periodic activation of i/o-0 to allow biasing of external contact swit ches. the contact switch state can be detected via i/o-1, -2, and -3, and the device can wake-up from either lp mode. cyclic sense is optimized and designed primarily for closed contact switch in order to minimize consumption via the contact pull-up resistor. principle a dedicated timer provides an opportunity to select a cyclic sense period from 3.0 to 512 ms (selection in timer b). at the end of the period, the i/o-0 will be activated for a duration of t _cson (spi selectable in init register, to 200 ? s, 400 ? s, 800 ? s, or 1.6 ms). the i/o-0 hs transistor or ls transistor can be activated. the selection is done by the state of i/o-0 prior to entering in lp mode. during the t -cson duration, the i/o-x?s are monitored. if one of them is high, the device will detect a wake-up. ( figure 26 ). cyclic sense period is selected by the spi configuration prior to entering lp mode. upon entering lp mode, the i/o-0 should be activated. the level of i/o-1 is sense during the i/o-0 active time, and is deglitched for a duration of typically 30 ? s. this means that i/o-1 should be in the expected state for a duration longer than the deglitch time. the diagram below ( figure 26 ) illustrates the cyclic sense operation, with i/o-0 hs active and i/o-1 wake-up at high level. figure 26. cyclic sense operation - sw itch to gnd, wake-up by open switch i/o-0 i/o-1 normal mode lp mode i/o-0 hs active in normal mode i/o-0 hs active during cyclic sense active time cyclic sense period cyclic sense active time reset or normal request mode wake-up detected. state of i/o-1 low => no wake-up cyclic sense active i/o-1 deglitcher time i/o-1 high => wake-up i/o-0 i/o-1 zoom time (ex 200 us) wake-up event detected i/o-0 i/o-1 s1 closed s1 open s1 (typically 30 us) s1 r i/o-2 r s2 r s3 i/o-3 i/o-0 i/o-1 s1 r i/o-2 r s2 r s3 i/o-3 upon entering in lp mode, all 3 contact switches are closed. in lp mode, 1 contact switch is open. high level is detected on i/o-x, and device wakes up.
analog integrated circuit device data ? 48 freescale semiconductor 33903/4/5 functional device operation cyclic int operation during lp vdd on mode cyclic int operation during lp vdd on mode principle this function can be used only in lp v dd on mode (lp v dd on). when cyclic int is selected and device is in lp v dd on mode, the device will generate a periodic int pulse. upon reception of the int pulse, the mcu must acknowledge the int by sending spi commands before the end of the next int period in order to keep the process going. when cyclic int is selected and operating, the device remains in lp v dd on mode, assuming the spi commands are issued properly. when no/improper spi commands are sent, the device will cease cyclic int operation and leave lp v dd on mode by issuing a reset. the device will then enter into normal request mode. vdd current capability and vdd regulator behavior is similar as in lp v dd on mode. operation cyclic int period selection: register timer b spi command in hex 0x56xx [example; 0x560e for 512ms cyclic interrupt period (spi command without parity bit)]. this command must be send while the device is in normal mode. spi commands to acknowledge int : (2 commands) - read the random code via the watchdog register address using the following command: mosi 0x1b00 device report on miso second byte the rndm code (miso bit 0-7). - write watchdog refresh comm and using the random code inverted: 0x5a rndb. these commands can occur at any time within the period. initial entry in lp mode with cyclic int : after the device is set in lp v dd on mode, with cyclic int enable, no spi command is necessary until the first int pulse occurs. the acknowledge process must start only after the 1st int pulse. leave lp mode with cyclic int: this is done by a spi wake-up command, similar to spi wake-up from lp v dd on mode: 0x5c10. the device will enter into normal request mode. improper spi command while cyclic int operates: when no/improper spi commands are sent, while the device is in lp v dd on mode with cyclic int enable, the device will cease cyclic int operation and leave lp v dd on mode by issuing a reset. the device will then enter into normal request mode. the figure below ( figure 27 ) describes the complete cyclic interrupt operation. figure 27. cyclic interrupt operation normal mode int spi timer b lp v dd cyclic int period cyclic int period lp v dd on mode on mode read rndm code write rndm code inv. 1st period 2nd period normal mode cyclic int period cyclic int period 3rd period spi wake-up: 0x5c10 write timer b, select cyclic int period (ex: 512 ms, 0x560e) write device mode: lp v dd on with cyclic int enable (example: 0x5c90) cyclic int period legend for spi commands int spi rst reset and request prepare lp v dd on in lp v dd on with cyclic int leave lp improper or no with cyclic int v dd on mode lp v dd on mode leave lp v dd on and cyclic int due to improper operation request acknowledge spi command normal mode
analog integrated circuit device data ? freescale semiconductor 49 33903/4/5 functional device operation behavior at power up and power down behavior at power up and power down device power up this section describe the device behavior during ramp up, and ramp down of v sup/1 , and the flexibility offered mainly by the crank bit and the two v dd under-voltage reset thresholds. the figures below illustrate the device behavior during v sup/1 ramp up. as the crank bit is by default set to 0, v dd is enabled when v sup/1 is above v sup th 1 parameters. figure 28. v dd start-up versus v sup/1 tramp device power down the figures below illustrate the device behavior during v sup/1 ramp down, based on crank bit configuration, and v dd under-voltage reset selection. crank bit reset (init watchdog register, bit 0 =0) bit 0 = 0 is the default st ate for this bit. during v sup/1 ramp down, v dd remain on until device enters in reset mode due to a v dd under-voltage condition (v dd < 4.6 v or v dd < 3.2 v typically, threshold selected by the spi). when device is in reset, if v sup/1 is below ?v sup_th1 ?, v dd is turned off. crank bit set (init watchd og register, bit 0 =1) the bit 0 is set by spi write. during v sup/1 ramp down, v dd remains on until device detects a por and set batfail. this occurs for a v sup/1 approx 3.0 v. d1 v bat vsup/1 v sup_th1 v sup_nominal (ex 12 v) v dd nominal (ex 5.0 v) vdd gnd v dd_start up v dd_off 90% v dd_start up 10% v dd_start up vdd vsup/1 i _vdd v sup slew rate 3390x v dd_uv th (typically 4.65 v) rst 1.0 ms
analog integrated circuit device data ? 50 freescale semiconductor 33903/4/5 functional device operation behavior at power up and power down figure 29. v dd behavior during v sup/1 ramp down v sup_nominal v dd (5.0 v) vdd vsup/1 rst (ex 12 v) v bat v dd_uv th (typically 4.65 v) v sup_th1 (4.1 v) v sup_nominal v dd (5.0 v) vdd vsup/1 rst (ex 12 v) v bat v dd_uv th (typically 4.65 v) v sup_th1 (4.1 v) int v dd_uv th2 (typically 3.2 v) v sup_nominal v dd (5.0 v) vdd vsup/1 rst (ex 12 v) v bat v dd_uv th (typically 4.65 v) int v dd_uv th2 (typically 3.2 v) batfail (3.0 v) (1) (2) (1) reset then (2) v dd turn off v sup_nominal v dd (5.0 v) vdd vsup/1 rst (ex 12 v) v bat v dd_uv th (typically 4.65 v) batfail (3.0 v) case 2: ?v dd uv 4.6v?, with bit crank = 1 case 1: ?v dd uv th 3.2v?, with bit crank = 0 (default value) case 2: ?v dd uv 3.2v?, with bit crank = 1 case 1: ?v dd uv th 4.6v?, with bit crank = 0 (default value)
analog integrated circuit device data ? freescale semiconductor 51 33903/4/5 fail-safe operation behavior at power up and power down fail-safe operation overview fail-safe mode is entered when specific fail conditions occur. the ?safe state? conditi on is defined by the resistor connected at the dgb pin. sa fe mode is entered after additional event or conditions are met: time out for can communication and state at i/o-1 pin. exiting the safe state is always possible by a wake-up event: in the safe state, th e device can automatically be awakened by can and i/o (if configured as inputs). upon wake-up, the device operation is resumed: enter in reset mode. fail-safe functionality upon dedicated event or i ssue detected at a device pin (i.e. rst short to vdd), the safe mode can be entered. in this mode, the safe pin is active low. description upon activation of the safe pin, and if the failure condition that make the safe pin activated have not recovered, the device can help to reduce ecu consumption, assuming that the mcu is not able to set the whole ecu in lp mode. two main cases are available: mode a upon safe activation, the mcu remains powered (v dd stays on), until the failure condition recovers (i.e. s/w is able to properly control the devic e and properly refresh the watchdog). modes b1, b2 and b3 upon safe activation, the syst em continues to monitor external event, and disable the mcu supply (turn v dd off). the external events monitored are: can traffic, i/o-1 low level or both of them. 3 sub cases exist, b1, b2 and b3. note: no can traffic indicates that the ecu of the vehicle are no longer active, thus that the car is being parked and stopped. the i/o low level detecti on can also indicate that the vehicle is being shutdown, if the i/o-1 pin is connected for instance to a switched battery signal (ignition key on/off signal). the selection of the monitored events is done by hardware, via the resistor con nected at dbg pin, but can be over written by software, via a specific spi command. by default, after power up the device detect the resistor value at dbg pin (upon transition from init to normal mode), and, if no specific spi command related to debug resistor change is send, operates according to the detected resistor. the init misc register allow you to verify and change the device behavior, to either confirm or change the hardware selected behavior. device will then operate according to the safe mode configured by the spi. table 9 illustrates the complete options available: exit of safe mode exit of the sa fe state with v dd off is always possible by a wake-up event: in this safe state the device can automatically awakened by can and i/o (if i/o wake-up was enable by the spi prior to enter into safe mode). upon wake-up, the device operation is resumed, and device enters in reset mode. the safe pin remains active, until there is a proper read and clear of the spi flags reporting the safe conditions. table 9. fail-safe options resistor at dbg pin spi coding - register init misc bits [2,1,0] (higher priority that resistor coding) safe mode code v dd status <6.0 k bits [2,1,0) = [111]: verification enable: resistor at dbg pin is typically 0 kohm (ra) - selection of safe mode a a remains on typically 15 k bits [2,1,0) = [110]: verification enable: resistor at dbg pin is typically 15 kohm (rb1) - selection of safe mode b1 b1 turn off 8.0 s after can traffic bus idle detection. typically 33 k bits [2,1,0) = [101]: verification enable: resistor at dbg pin is typically 33 kohm (rb2 - selection of safe mode b2 b2 turn off when i/o-1 low level detected. typically 68 k bits [2,1,0) = [100]: verification enable: resistor at dbg pin is typically 68 kohm (rb3) - selection of safe mode b3 b3 turn off 8.0 s after can traffic bus idle detection and when i/o-1 low level detected.
analog integrated circuit device data ? 52 freescale semiconductor 33903/4/5 fail-safe operation behavior at power up and power down . figure 30. safe operation flow chart conditions to set sa fe pin active low watchdog refresh issue: safe activated at 1st reset pulse or at the second consecutive re set pulse (selected by bit 4, init watchdog register). v dd low: v dd < r st-th . safe pin is set low at the same time as the rst pin is set low. the rst pin is monitored to verify that reset is not clamped to a low level preventin g the mcu to operate. if this is the case, the safe mode is entered. watchdog failure v dd low: rst s/c gnd: - safe low 8 consecutive watchdog failure (5) state a: r dbg <6.0 k and - safe low - reset: 1.0 ms - v dd on - reset low init, b) ecu external signal state b1: r dbg =15k and state b3: state b2: - safe low - reset low - v dd off a) evaluation of bus idle timeout expired normal, flash v dd 100 ms device state: reset nr bit 4, init watchdog = 1 (1) detection of 2nd consecutive watchdog failure safe low safe high safe low reset: 1.0 ms pulse bit 4, init watchdog = 0 (1) reset: 1.0 ms pulse normal request power up, or spi at dbg pin during reset safe pin release failure recovery, safe pin remains low spi (3) and bus idle time out expired reset wake-up (2), v dd on, safe pin remains low register content (safe high) failure events 1) bit 4 of init watchdog register 2) wake-up event: can, lin or i/o-1 high level (if i/o-1 wake-up previously enabled) 3) spi commands: 0xdd00 or 0x dd80 to release safe pin 4) recovery: reset low condition released, v dd low condition released, correct spi watchdog refresh 5) detection of 8 consecutive watchdog failures: no correct spi watchdog refresh command occurred for duration of 8 x 256 ms. 6) dynamic behavior: 1.0 ms reset pulse every 256 ms, due to no watchdog refresh spi command, and device state transition legend: r dbg = 33 k and i/o-1 low r dbg = 47 k and i/o-1 low - v dd on (6) - safe low - v dd on - reset low periodic pulse state a: r dbg <6.0 k and watchdog failure (v dd low or r st s/c gnd) failure safe state a safe state b resistor detected between reset and normal request mode, or init reset and init modes. - bus idle time out - i/o-1 monitoring monitoring (7): 7) 8 second timer for bus idle timeout. i/o-1 high to low transition. safe operation flow chart
analog integrated circuit device data ? freescale semiconductor 53 33903/4/5 fail-safe operation behavior at power up and power down safe mode a illustration figure 31 illustrates the event and consequences when safe mode a is selected via the appropriate debug resistor or spi configuration. figure 31. safe mode a behavior illustration rst v dd failure event, i.e. watchdog safe off state on state 8 x 256 ms delay time to enter in safe mode v dd rst safe to evaluate resistor at dbg pin and monitor ecu external events 1st 8th 2nd behavior illustration for safe state a (r dg < 6.0 kohm), or selection by the spi step 1: failure illustration rst v dd failure event, v dd low safe off state on state 100 ms delay time to enter in safe mode to evaluate resistor at dbg pin and monitor ecu external events v dd_uv th 100ms v dd rst safe v dd < v dd_uv th gnd gnd rst v dd failure event, reset s/c gnd safe off state on state 100 ms deglitcher time to activate safe and enter in safe mode to evaluate resistor at the dbg pin and monitor ecu external events 2.5 v 100ms v dd rst safe step 2: consequence on v dd , rst and safe
analog integrated circuit device data ? 54 freescale semiconductor 33903/4/5 fail-safe operation behavior at power up and power down safe mode b1, b2 and b3 illustration figure 32 illustrates the event, and consequences when safe mode b1, b2, or b3 is selected via the appropriate debug resistor or spi configuration. figure 32. safe modes b1, b2 , or b3 behavior illustration dbg resistor => safe state b1 v dd rst safe can bus can bus idle time i/o-1 i/o-1 high to low transition dbg resistor => safe state b2 dbg resistor => safe state b3 can bus can bus idle time i/o-1 i/o-1 high to low transition step 2: rst v dd failure event, i.e. watchdog safe off state on state 8 x 256 ms delay time to enter in safe mode to evaluate resistor at the dbg pin and monitor ecu external events 1st 8th 2nd step 1: failure illustration rst v dd failure event, v dd low safe off state on state 100 ms delay time to enter in safe mode to evaluate resistor at dbg pin and monitor ecu external events v dd_uv th 100 ms gnd rst v dd failure event, reset s/c gnd safe off state on state 100 ms deglitcher time to activate safe and enter in safe mode to evaluate resistor at dbg pin and monitor ecu external events 2.5 v 100 ms v dd rst safe v dd off rst safe v dd if v dd failure recovered v dd < v dd_uv th v dd off gnd step 3: consequences for v dd if reset s/c gnd recovered behavior illustration for the safe state b (r dg > 10 kohm) wake - up ecu e x ternal c on di ti o n met => v dd di s a ble ecu external event to r dbg resistor or disable v dd based on spi configuration exclusive detection of
analog integrated circuit device data ? freescale semiconductor 55 33903/4/5 can interface can interface description can interface can interface description the figure below is a high level schematic of the can interface. it exist in a ls dr iver between canl and gnd, and a hs driver from canh to 5 v-can. two differential receivers are connected between canh and canl to detect a bus state and to wake-up from can sleep mode. an internal 2.5 v reference provides the 2.5 v recessive levels via the matched r in resistors. the resist ors can be switched to gnd in can sleep mode. a de dicated split buffer provides a low-impedance 2.5 v to the split pin, for recessive level stabilization. figure 33. can interface block diagram can interface supply the supply voltage for the can driver is the 5 v-can pin. the can interface also has a supply pass from the battery line through the vsup/2 pin. this pass is used in can sleep mode to allow wake-up detection. during can communication (transmission and reception), the can interface current is sourced from the 5 v-can pin. during can lp mode, the current is sourced from the vsup/ 2 pin. txd/rxd mode in txd/rxd mode, both the can driver and the receiver are on. in this mode, the can lines are controlled by the txd pin level and the can bus stat e is reported on the rxd pin. the 5 v-can regulator must be on. it supplies the can driver and receiver.the split pin is active and a 2.5 v biasing is provided on the split output pin. receive only mode this mode is used to disable the can driver, but leave the can receiver active. in this mode, the device is only able to report the can state on the rxd pin. the txd pin has no effect on can bus lines. the 5 v-can regulator must be on. the split pin is active and a 2.5 v biasing is provided on the split output pin. operation in txd/rxd mode the can driver will be enabled as soon as the device is in normal mode and the txd pin is recessive. differential receiver driver driver 2.5 v receiver pattern detection canh canl qh ql r in r in vsup/2 5v-can failure detection buffer 5v-can split wake-up & management txd rxd 5v-can thermal spi & state machine spi & state machine spi & state machine
analog integrated circuit device data ? 56 freescale semiconductor 33903/4/5 can interface can interface description when the can interface is in normal mode, the driver has two states: recessive or dominant. the driver state is controlled by the txd pin. the bus state is reported through the rxd pin. when txd is high, the driver is set in the recessive state, and canh and canl lines are biased to the voltage set with 5 v-can divided by 2, or approx. 2.5 v. when txd is low, the bus is set into the dominant state, and canl and canh drivers are active. canl is pulled low and canh is pulled high. the rxd pin reports the bus state: canh minus the canl voltage is compared versus an internal threshold (a few hundred mv). if ?canh minus canl? is below the threshold, the bus is recessive and rxd is set high. if ?canh minus canl? is above the threshold, the bus is dominant and rxd is set low. the split pin is active and provides a 2.5 v biasing to the split output. txd/rxd mode and sl ew rate selection the can signal slew rate selection is done via the spi. by default and if no spi is used, t he device is in the fastest slew rate. three slew rates are available. the slew rate controls the recessive to dominant, and dominant to recessive transitions. this also affects the delay time from the txd pin to the bus and from the bus to the rxd. the loop time is thus affected by the sl ew rate selection. minimum baud rate the minimum baud rate is determined by the shortest txd permanent dominant timing detection. the maximum number of consecutive dominant bits in a frame is 12 (6 bits of active error flag and its echo error flag). the shortest txd dominant detection time of 300 ? s lead to a single bit time of: 300 ? s / 12 = 25 ? s. so the minimum baud rate is 1 / 25 ? s = 40 kbaud. sleep mode sleep mode is a reduced current consumption mode. canh and canl drivers are disabled and canh and canl lines are terminated to gnd via the r in resistor, the split pin is high-impedance. in order to monitor bus activities, the can wake-up receiver can be enabled. it is supplied internally from v sup/2 . wake-up events occurring on the can bus pin are reporting by dedicated flags in spi and by int pulse, and results in a device wake-up if the device was in lp mode. when the device is set back into normal mode, canh and canl are set back into the recessive level. this is illustrated in figure 34 . . figure 34. bus signal in txd/rxd and lp mode wake-up when the can interface is in sleep mode with wake-up enabled, the can bus traffic is detected. the can bus wake- up is a pattern wake-up. the wake-up by the can is enabled or disabled via the spi. canl canh txd rxd 2.5 v canl-dom canh-dom canl/canh-rec 2.5 v high ohmic termination (50 kohm) to gnd split dominant state recessive state bus driver receiver (bus dominant set by other ic) high-impedance normal or listen only mode normal or listen only mode go to sleep, canh-canl sleep or stand-by mode
analog integrated circuit device data ? freescale semiconductor 57 33903/4/5 can interface can interface description figure 35. single dominant pulse wake-up pattern wake-up in order to wake-up the can interface, the wake-up receiver must receive a series of three consecutive valid dominant pulses, by default when the canwu bit is low. canwu bit can be set high by spi and the wake-up will occur after a single pulse duration of 2.0 ? s (typically). a valid dominant pulse should be longer than 500 ns. the three pulses should occur in a time frame of 120 ? s, to be considered valid. when three pulses meet these conditions, the wake signal is detected. this is illustrated by the following figure. . figure 36. pattern wake-up - multiple dominant detection bus termination the device supports the two main types of bus terminations: ? differential termination resistors between canh and canl lines. ? split termination concept, with the mid point of the differential termination co nnected to gnd through a capacitor and to the split pin. ? in application, the device can also be used without termination. ? figure 37 illustrates some of the most common terminations. canl canh internal wake-up signal dominant can pulse # 1 dominant pulse # 2 t can wu1-f can wake-up detected bus internal differential wake-up receiver signal canl canh internal wake-up signal dominant internal differential wake-up receiver signal can pulse # 1 dominant pulse # 2 dominant pulse # 3 dominant pulse # 4 t can wu3-f t can wu3-f t can wu3-f t can wu3-to dominant pulse # n: duration 1 or multiple dominant bits can wake-up detected bus
analog integrated circuit device data ? 58 freescale semiconductor 33903/4/5 can interface can bus fault diagnostic figure 37. bus termination options can bus fault diagnostic the device includes diagnostic of bus short-circuit to gnd, vbat, and internal ecu 5.0 v. several comparators are implemented on canh and canl lines. these comparators monitor the bus level in the re cessive and dominant states. the information is then managed by a logic circuitry to properly determine the failure and report it. figure 38. can bus simpli fied structure truth tabl e for failure detection the following table indicates the state of the comparators when there is a bus fa ilure, and depending upon the driver state. canh canl split can bus 60 60 standard termination canh canl split can bus 120 no connect canh canl split no termination no connect ecu connector ecu connector can bus ecu connector table 10. failure detection truth table failure description driver recessive state driver dominant state lg (threshold 1.75 v) hg (threshold 1.75 v) lg (threshold 1.75 v) hg (threshold 1.75 v) no failure 1 1 0 1 canl to gnd 0 0 0 1 canh to gnd 0 0 0 0 lb (threshold v sup -2.0 v) hb (threshold v sup -2.0 v) lb (threshold v sup -2.0 v) hb (threshold v sup -2.0 v) no failure 0 0 0 0 canl to vbat 1 1 1 1 canh to vbat 1 1 0 1 hg canh canl lg v dd vrg vrg hb vrvb lb vrvb logic txd diag v dd (5.0 v) gnd (0.0 v) recessive level (2.5 v) v bat (12-14 v) v rvb (v sup -2.0 v) v rg (1.75 v) canl dominant level (1.4 v) canh dominant level (3.6 v) l5 vr5 h5 vr5 v r5 (v dd -.43 v)
analog integrated circuit device data ? freescale semiconductor 59 33903/4/5 can interface can bus fault diagnostic detection principle in the recessive state, if one of the two bus lines are shorted to gnd, vdd (5.0 v), or vbat, the voltage at the other line follows the shorted lin e, due to the bus termination resistance. for example: if ca nl is shorted to gnd, the canl voltage is zero, the canh voltage measured by the hg comparator is also close to zero. in the recessive state, the failure detection to gnd or vbat is possible. however, it is not possible with the above implementation to distinguish which of the canl or canh lines are shorted to gnd or vbat. a complete diagnostic is possible once the driver is turned on, and in the dominant state. number of samples for proper failure detection the failure detector requires at least one cycle of the recessive and dominant states to properly recognize the bus failure. the erro r will be fully detected a fter five cycles of the recessive-dominant states. as long as the failure detection circuitry has not detected the same error for five recessive- dominant cycles, the error is not reported. bus clamping detection if the bus is detected to be in dominant for a time longer than (t dom ), the bus failure flag is set and the error is reported in the spi. this condition could occur when the canh line is shorted to a high-voltage. in this case, current will flow from the high- voltage short-circuit, through the bus termination resistors (60 ? ), into the split pin (if used), and into the device canh and canl input resistors, which are terminated to internal 2.5 v biasing or to gnd (sleep mode). depending upon the high-voltage short-circuit, the number of nodes, usage of the split pin, r in actual resistor and mode state (sleep or active) the voltage across the bus termination can be sufficient to create a positive dominant voltage between canh and canl, and the rxd pin will be low. this would prevent start of any can communication and thus, proper failure identification requires five pulses on txd. the bus dominant clamp circuit will help to determine such failure situation. rxd permanent recessive failure (does not apply to ?c version?) the aim of this detection is to diagnose an external hardware failure at the rxd output pin and ensure that a permanent failure at rxd does not disturb the network communication. if rxd is shorted to a logic high signal, the can protocol module within the mcu will not recognize any incoming message. in addition, it will not be able to easily distinguish the bus idle state and can start communication at any time. in order to prevent this, rxd failure detection is necessary. when a failure is detected, the rxd high flag is set and can switches to receive only mode. figure 39. rxd path simplifie d schematic, rxd short to v dd detection implementation for detection the implementation senses the rxd output voltage at each low to high transition of the differential receiver. excluding the internal propagation delay, the rxd output should be low when the differen tial receiver is low. when an external short to vdd at the rxd output, rxd will be tied to a high level and can be detected at the next low to high transition of the differential receiver. as soon as the rxd permanent recessive is detected, the rxd driver is deactivated. l5 (threshold v dd -0.43 v) h5 (threshold v dd -0.43 v) l5 (threshold v dd -0.43 v) h5 (threshold v dd -0.43 v) no failure 0 0 0 0 canl to 5.0 v 1 1 1 1 canh to 5.0 v 1 1 0 1 table 10. failure detection truth table failure description driver recessive state driver dominant state lg (threshold 1.75 v) hg (threshold 1.75 v) lg (threshold 1.75 v) hg (threshold 1.75 v) canh canl diff v dd rxsense rxd driver rxd txd txd driver 60 v dd logic diag canl&h diff output rxd output rxd short to v dd prop delay rxd flag rxd flag latched v dd /2 sampling sampling the rxd flag is not the rxpr bit in the lpc register, and neither is the canf in the intr register.
analog integrated circuit device data ? 60 freescale semiconductor 33903/4/5 can interface can bus fault diagnostic once the error is detected the driver is disabled and the error is reported via spi in can register. recovery condition the internal recovery is done by sampling a correct low level at txd as shown in the following illustration. figure 40. rxd path simplifie d schematic, rxd short to v dd detection txd permanent dominant principle if the txd is set to a permanent low level, the can bus is set into dominant level, and no communication is possible. the device has a txd permanent timeout detector. after the timeout (t dout ), the bus driver is disabled and the bus is released into a recessive state. the txd permanent flag is set. recovery the txd permanent dominant is used and activated when there is a txd short to rxd. the recovery condition for a txd permanent dominant (recovery means the re-activation of the can drivers) is done by entering into a normal mode controlled by the mcu or when txd is recessive while rxd change from recessive to dominant. txd to rxd short-circuit principle when txd is shorted to rx d during incoming dominant information, rxd is set to low. consequently, the txd pin is low and drives canh and canl into a dominant state. thus the bus is stuck in dominant. no further communication is possible. detection and recovery the txd permanent dominant timeout will be activated and release the canl and canh drivers. however, at the next incoming dominant bit, the bus will then be stuck in dominant again. the recovery condition is same as the txd dominant failure important information for bus driver reactivation the driver stays disabled until the failure is/are removed (txd and/or rxd is no longer permanent dominant or recessive state or shorted) and the failure flags cleared (read). the can driver must be set by spi in txd/rxd mode in order to re enable the can bus driver. canl&h diff output rxd output rxd short to v dd rxd flag rxd flag latched sampling sampling the rxd flag is not the rxpr bit in the lpc register , and neither is the canf in the intr register. rxd no longer shorted to v dd
analog integrated circuit device data ? freescale semiconductor 61 33903/4/5 lin block lin interface description lin block lin interface description the physical interface is dedicated to automotive lin sub- bus applications. the interface has 20 kbps and 10 kbps baud rates, and includes as well as a fast baud rate for test and programming modes. it has excellent esd robustness and immunity against disturbance, and radiated emission performance. it has safe behavior when a lin bus short-to-ground, or a lin bus leakage during lp mode. digital inputs are related to the device vdd pin. power supply pin (vsup/2) the vsup/2 pin is the supply pin for the lin interface. to avoid a false bus message, an under-voltage on vsup/2 disables the transmission path (from txd to lin) when ? v sup/2 falls below 6.1 v. ground pin (gnd) when there is a ground disconnection at the module level, the lin interface do not have si gnificant current consumption on the lin bus pin when in the recessive state. lin bus pin (lin, lin1, lin2) the lin pin represents the single-wire bus transmitter and receiver. it is suited for auto motive bus systems, and is compliant to the lin bus s pecification 2.1 and saej2602-2. the lin interface is only active during normal mode. driver characteristics the lin driver is a ls mosfet with internal over-current thermal shutdown. an internal pull-up resistor with a serial diode structure is integrated so no external pull-up components are required for the application in a slave node. an additional pull-up resistor of 1.0 k ? must be added when the device is used in th e master node. the 1.0 k ?? pull-up resistor can be connected to the lin pin or to the ecu battery supply. the lin pin exhibits no reverse current from the lin bus line to v sup/2 , even in the event of a gnd shift or v sup/2 disconnection. the transmitter has a 20 kbps, 10 kbps and fast baud rate, which are selected by spi. receiver characteristics the receiver thresholds are ratiometric with the device v sup/2 voltage. if the v sup/2 voltage goes below typically 6.1 v, the lin bus enters into a re cessive state even if communication is sent on txd. if lin driver temperature r eaches the over-temperature threshold, the transceiver and receiver are disabled. when the temperature falls below t he over-temperature threshold, lin driver and receiver will be automatically enabled. data input pin (txd-l, txd-l1, txd-l2) the txd-l,txd-l1 and txd- l2 input pin is the mcu interface to control the state of the lin output. when txd-l is low (dominant), lin output is low. when txd-l is high (recessive), the lin output transistor is turned off. this pin has an internal pull-up current source to v dd to force the recessive state if the input pin is left floating. if the pin stays low (dominant sate) more than t txddom , the lin transmitter goes automatically in recessive state. this is reported by flag in lin register. data output pin (rxd-l, rxd-l1, rxd-l2) this output pin is the mcu in terface, which reports the state of the lin bus voltage. lin high (recessive) is reported by a high voltage on rxd, lin low (dominant) is reported by a low voltage on rxd. lin operational modes the lin interface have two operational modes, transmit receiver and lin disable modes. transmit receive in the txd/rxd mode, the lin bus can transmit and receive information. when the 20 kbps baud rate is selected, the slew rate and timing are compatible with lin protocol specification 2.1. when the 10 kbps baud rate is selected, the slew rate and timing are compatible with j2602-2. when the fast baud rate is selected, the slew rate and timing are much faster than the above specification and allow fast data transition. the lin in terface can be set by the spi command in txd/rxd mode, only when txd-l is at a high level. when the spi command is send while txd-l is low, the command is ignored. sleep mode this mode is selected by spi , and the transmission path is disabled. supply current for lin block from v sup/2 is very low (typically 3.0 ? a). lin bus is monitor to detect wake-up
analog integrated circuit device data ? 62 freescale semiconductor 33903/4/5 lin block lin operational modes event. in the sleep mode, the internal 725 kohm pull-up resistor is connected and the 30 kohm disconnected. the lin block can be awakened from sleep mode by detection of lin bus activity. lin bus activity detection the lin bus wake-up is recognized by a recessive to dominant transition, followed by a dominant level with a duration greater than 70 ? s, followed by a dominant to recessive transition. this is illustrated in figures 20 and 21 . once the wake-up is detected, the event is reported to the device state machine. an int is generated if the device is in lp v dd on mode, or v dd will restart if the device was in lp v dd off mode. the wake-up can be enable or disable by the spi. fail-safe features table 11 describes the lin block behavior when there is a failure. table 11. lin block failure fault functionnal mode condition consequence recovery lin supply under-voltage txd rxd lin supply voltage < 6.0 v (typically) lin transmitter in recessive state condition gone txd pin permanent dominant txd pin low for more than t txddom lin transmitter in recessive state condition gone lin thermal shutdown txd rxd lin driver temperature > 160 c (typically) lin transmitter and receiver disabled hs turned off condition gone
analog integrated circuit device data ? freescale semiconductor 63 33903/4/5 serial peripheral interface high level overview serial peripheral interface high level overview the device uses a 16 bits spi, with the following arrangements: mosi, master out slave in bits: ? bits 15 and 14 (called c1 and c0) are control bits to select the spi operation mode (write control bit to device register, read back of the control bits, read of device flag). ? bit 13 to 9 (a4 to a0) to select the register address. ? bit 8 (p/n) has two functions: parity bit in write mode (optional, = 0 if not used), next bit ( = 1) in read mode. ? bit 7 to 0 (d7 to d0): control bits miso, master in slave out bits: ? bits 15 to 8 (s15 to s8) are device status bits ? bits 7 to 0 (do7 to do0) are either extended device status bits, device internal control register content or device flags. the spi implementation does not support daisy chain capability. figure 41 is an overview of the spi implementation. figure 41. spi overview bit 15 bit 13 bit 11 bit 12 bit 10 bit 14 bit 9 bit 8 c1 a4 a2 c0 bit 7 bit 5 bit 3 bit 4 bit 2 bit 6 bit 1 bit 0 d7 d5 d3 d4 d2 d6 d1 d0 control bits a3 register address parity (optional) or a0 a1 p/n data mosi s15 s13 s11 s14 do7 do5 do3 do4 do2 do6 do1 do0 s12 s9 s10 s8 miso device status extended device status, register control bits or device flags next bit = 1 cs sclk mosi miso tri-state tri-state spi wave form, and signals polarity s15 s14 do0 c1 c0 d0 sclk signal is low outside of cs active cs active low. must rise at end of 16 clocks, mosi and miso data changed at sclk rising edge and sampled at falling edge. msb first. miso tri-state outside of cs active don?t care don?t care for write commands, mosi bits [15, 14] = [0, 1]
analog integrated circuit device data ? 64 freescale semiconductor 33903/4/5 serial peripheral interface detail operation detail operation spi operation deviation (does not apply to ?c? version) in some cases, the spi write command is not properly interpreted by the device. this results in either a ?non received spi command? or a ?corrupted spi command?. important : due to this, the t lead and t cs low parameters must be carefully acknowledged. only spi write commands (starting with bits 15,14 = 01) are affected. the spi read commands (starting with bits 15,14 = 00 or 11) are not affected. the occurrence of this issu e is extremely low and is caused by the synchronization between internal and external signals. in order to guarantee proper operation, the following steps must be taken. 1. ensure the duration of the chip select low (t cs low ) state is >5.5 ? s. note: in data sheet revisions prio r to 7.0, this parameter is not specified and is indirectly defined by the sum of 3 parameters, t lead + 16 x t pclk + t lag (sum = 4.06 ? s). 2. ensure spi timing parameter t lead is a min. of 550 ns . note: in data sheet revisions prior to 7.0, the t lead parameter is a min of 30 ns. 3. make sure to include a spi read command after a spi write command. in case a series of spi wr ite commands is used, only one additional spi read is necessary. the recommended spi read command is ?device id read: 0x2580? so device operation is not affected (e x: clear flag). other spi read commands may also be used. when the previous steps are implemented, the device will operate as follows: for a given spi write command (named spi write ?n?): ? in case the spi write comman d ?n? is not accepted, the following spi command (named spi ?n+1?) will finish the write process of the spi write ?n?, thanks to step 2 (t lag > 550 ns) and step 3 (which is the additional spi command ?n+1?). ? by applying steps 1, 2, and 3, no spi command is ignored. worst case, the spi write ?n? is executed at the time the spi ?n+1? is sent. this will lead to a delay in device operation (delay between spi command ?n? and ?n+1?). note: occurrence of an incorrect command is reduced, thanks to step 1 (extension of t cs low duration to >5.5 ? s). sequence examples: example 1: ? 0x60c0 (can interface control) ? in case this command is missed, next write command will complete it ? 0x66c0 (lin interface control) ? in case this command is missed, next read command will complete it ? 0x2580 (read device id) ? additional command to complete previous lin command, in case it was missed example 2: ? 0x60c0 (can interface control) - in case this command is missed, next write command will complete it ? 0x66c0 (lin interface control) - in case this command is missed, next read command will complete it ? 0x2100 (read can register content) ? this command will complete previous one, in case it was missed ? 0x2700 (read lin register content) bits 15, 14, and 8 functions table 12 summarizes the various spi operation, depending upon bit 15, 14, and 8. table 12. spi operations (bits 8, 14, & 15) control bits mosi[15-14], c1-c0 type of command parity/next mosi[8] p/n note for bit 8 p/n 00 read back of register content and block (can, i/o, int, lins) real time state. see table 39 . 1 bit 8 must be set to 1, inde pendently of the parity function selected or not selected. 01 write to register address, to control the device operation 0 if bit 8 is set to ?0?: means parity not selected or parity is selected and parity = 0 1 if bit 8 is set to ?1?: means parity is selected and parity = 1 10 reserved 11 read of device flags form a register address 1 bit 8 must be set to 1, inde pendently of the parity function selected or not selected.
analog integrated circuit device data ? freescale semiconductor 65 33903/4/5 serial peripheral interface detail operation bits 13-9 functions the device contains several registers coded on five bits (bits 13 to 9). each register controls or reports part of the device?s function. data can be written to the register to control the device operation or to set the default value or behavior. every register can also be read back in order to ensure that it?s content (def ault setting or value previously written) is correct. in addition, some of the registers are used to report device flags. device status on miso when a write operation is performed to store data or control bits into the device, the miso pin reports a 16 bit fixed device status composed of 2 byte s: device fixed status (bits 15 to 8) + extended device status (bits 7 to 0). in a read operation, miso will report the fixed device status (bits 15 to 8) and the next eight bits will be the content of the selected register. register adress table table 13 is a list of device registers and addresses, coded with bits 13 to 9. table 13. device registers with corresponding address address mosi[13-9] a4...a0 description quick ref. name functionality 0_0000 analog multiplexer mux 1) write ?device control bits? to register address. 2) read back register ?control bits? 0_0001 memory byte a ram_a 1) write ?data byte? to register address. 2) read back ?data byte? from register address 0_0010 memory byte b ram_b 0_0011 memory byte c ram_c 0_0100 memory byte d ram_d 0_0101 initialization regulators init reg 1) write ?device initialization control bits? to register address. 2) read back ?initialization control bits? from register address 0_0110 initialization watchdog init watchdog 0_0111 initialization lin and i/o init lin i/o 0_1000 initialization miscellaneous functions init misc 0_1001 specific modes spe_mode 1) write to register to select dev ice specific mode, using ?inverted random code?. 2) read ?random code? 0_1010 timer_a: watchdog & lp mcu consumption tim_a 1) write ?timing values? to register address. 2) read back register ?timing values? 0_1011 timer_b: cyclic sense & cyclic interrupt tim_b 0_1100 timer_c: watchdog lp & forced wake-up tim_c 0_1101 watchdog refresh watchdog watchdog refresh commands 0_1110 mode register mode 1) write to register to select lp mode, with optional ?inverted random code? and select wake-up functionality 2) read operations: read back device ?current mode? read ?random code?, leave ?debug mode? 0_1111 regulator control reg 1) write ?device control bits? to register address, to select device operation. 2) read back register ?control bits?. 3) read device flags from each of the register addresses. 1_0000 can interface control can 1_0001 input output control i/o 1_0010 interrupt control interrupt 1_0011 lin1 interface control lin1 1_0100 lin2 interface control lin2
analog integrated circuit device data ? 66 freescale semiconductor 33903/4/5 serial peripheral interface detail operation complete spi operation table 14 is a compiled view of all the spi capabilities and options. both mosi and miso information are described. note: p = 0 if parity bit is not selected or parity = 0. p = 1 if parity is selected and parity = 1. parity bit 8 calculation the parity is used for the write-to-register command (bit 15,14 = 01). it is calculated based on the number of logic one contained in bits 15-9,7-0 sequence (this is the entire 16 bits of the write command except bit 8). bit 8 must be set to 0 if the number of 1 is odd. bit 8 must be set to 1if the number of 1 is even. examples 1: mosi [bit 15-0] = 01 00 011 p 01101001, p should be 0, because the command contains 7 bits with logic 1. thus the exact command will then be: mosi [bit 15-0] = 01 00 011 0 01101001 examples 2: mosi [bit 15-0] = 01 00 011 p 0100 0000, p should be 1, because the command contains 4 bits with logic 1. thus the exact command will then be: mosi [bit 15-0] = 01 00 011 1 0100 0000 parity function selection all spi commands and exam ples do not use parity functions. the parity function is optional. it is selected by bit 6 in init misc register. if parity function is not selected (bit 6 of init misc = 0), then parity bits in all spi commands (bit 8) must be ?0?. table 14. spi capabilities with options type of command mosi/ miso control bits [15-14] address [13-9] parity/next bits [8] bit 7 bits [6-0] read back of ?device control bits? (mosi bit 7 = 0) or read specific device information (mosi bit 7 = 1) mosi 00 address 1 0 000 0000 miso device fixed status (8 bits) register control bits content mosi 00 address 1 1 000 0000 miso device fixed status (8 bits) device id and i/os state write device control bit to address selected by bits (13-9). miso return 16 bits device status mosi 01 address (note) control bits miso device fixed status (8 bits) device extended status (8 bits) reserved mosi 10 reserved miso reserved read device flags and wake-up flags, from register address (bit 13-9), and sub address (bit 7). miso return fixed device status (bit 15-8) + flags from the selected address and sub-address. miso 11 address reserved 0 read of device flags form a register address, and sub address low (bit 7) mosi device fixed status (8 bits) flags miso 11 address 1 1 read of device flags form a register address, and sub address high (bit 7) mosi device fixed status (8 bits) flags
analog integrated circuit device data ? freescale semiconductor 67 33903/4/5 serial peripheral interface detail of control bits and register mapping detail of control bits and register mapping the following tables contain register bit meaning arranged by register address, from address 0_000 to address 1_0100 mux and ram registers table 15. mux register (38) mosi first byte [15-8] [b_15 b_14] 0_0000 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 00 _ 000 p mux_2 mux_1 mux_0 int 2k i/o-att 0 0 0 default state 0 0 0 0 0 0 0 0 condition for default por, 5 v-can off, any mode different from normal bits description b7 b6 b5 mux_2, mux_1, mux_0 - selection of external input signal or inte rnal signal to be measured at mux-out pin 000 all functions disable. no output voltage at mux-out pin 001 v dd regulator current recopy. ratio is approx 1/97. require s an external resistor or selection of internal 2.0 k (bit 3) 010 device internal voltage reference (approx 2.5 v) 011 device internal temperature sensor voltage 100 voltage at i/o-0. attenuation or gain is selected by bit 3. 101 voltage at i/o-1. attenuation or gain is selected by bit 3. 110 voltage at vsup/1 pin. refer to electrical table for attenuation ratio (approx 5) 111 voltage at vsense pin. refer to electrical table for attenuation ratio (approx 5) b4 int 2k - select device internal 2.0 kohm resistor between amux and gnd. this resistor allows the measurement of a voltage proportional to the v dd output current. 0 internal 2.0 kohm resistor disable. an external resi stor must be connected between amux and gnd. 1 internal 2.0 kohm resistor enable. b3 i/o-att - when i/o-0 (or i/o-1) is selected with b7,b6,b5 = 100 (or 101), b3 selects attenuation or gain between i/o-0 (or i/o-1) and mux-out pin 0 gain is approx 2 for device with v dd = 5.0 v (ref. to electrical table for exact gain value) gain is approx 1.3 for device with v dd = 3.3 v (ref. to electrical table for exact gain value) 1 attenuation is approx 4 for device with v dd = 5.0 v (ref. to electrical table for exact attenuation value) attenuation is approx 6 for device with v dd = 3.3 v (ref. to electrical table for exact attenuation value) notes 38. the mux register can be written and read only when the 5v-can regulator is on. if the mux register is written or read while 5v-can is off, the command is ignored, and the mxu register content is reset to default st ate (all control bits = 0).
analog integrated circuit device data ? 68 freescale semiconductor 33903/4/5 serial peripheral interface detail of control bits and register mapping table 16. internal memory registers a, b, c, and d, ram_a, ram_b, ram_c, and ram_d mosi first byte [15-8] [b_15 b_14] 0_0xxx [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 00 _ 001 p ram a7 ram a6 ram a5 ram a4 ram a3 ram a2 ram a1 ram a0 default state 0 0 0 0 0 0 0 0 condition for default por 01 00 _ 010 p ram b7 ram b6 ram b5 ram b4 ram b3 ram b2 ram b1 ram b0 default state 0 0 0 0 0 0 0 0 condition for default por 01 00 _ 011 p ram c7 ram c6 ram c5 ram c4 ram c3 ram c2 ram c1 ram c0 default state 0 0 0 0 0 0 0 0 condition for default por 01 00 _ 100 p ram d7 ram d6 ram d5 ram d4 ram d3 ram d2 ram d1 ram d0 default state 0 0 0 0 0 0 0 0 condition for default por
analog integrated circuit device data ? freescale semiconductor 69 33903/4/5 serial peripheral interface detail of control bits and register mapping init registers note: these registers can be written only in init mode table 17. initialization regulator registers, init reg (n ote: register can be written only in init mode) mosi first byte [15-8] [b_15 b_14] 0_0101 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 00 _ 101 p i/o-x sync v ddl rst[1] v ddl rst[0] v dd rstd[1] v dd rstd[0] v aux 5/3 cyclic on[1] cyclic on[0] default state 1 0 0 0 0 0 0 0 condition for default por bit description b7 i/o-x sync - determine if i/o-1 is sensed during i/o-0 ac tivation, when cyclic sense function is selected 0 i/o-1 sense anytime 1 i/o-1 sense during i/o-0 activation b6, b5 v ddl rst [1] v ddl rst [0] - select the v dd under-voltage threshold, to activate rst pin and/or int 00 reset at approx 0.9 v dd . 01 int at approx 0.9 v dd , reset at approx 0.7 v dd 10 reset at approx 0.7 v dd 11 reset at approx 0.9 v dd . b4, b3 v dd rst d[1] v dd rst d[0] - select the rst pin low lev duration, after v dd rises above the v dd under-voltage threshold 00 1.0 ms 01 5.0 ms 10 10 ms 11 20 ms b2 [v aux 5/3] - select vauxilary output voltage 0 v aux = 3.3 v 1 v aux = 5.0 v b1, b0 cyclic on[1] cyclic on[0] - determine i/o-0 activation time, when cyclic sense function is selected 00 200 ? s (typical value. ref. to dynamic parameters for exact value) 01 400 ? s (typical value. ref. to dynamic parameters for exact value) 10 800 ? s (typical value. ref. to dynamic parameters for exact value) 11 1600 ? s (typical value. ref. to dyna mic parameters for exact value)
analog integrated circuit device data ? 70 freescale semiconductor 33903/4/5 serial peripheral interface detail of control bits and register mapping table 18. initialization watchdog register s, init watchdog (note: register can be written only in init mode) mosi first byte [15-8] [b_15 b_14] 0_0110 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 00 _ 110 p wd2int mcu_oc oc-tim wd safe wd_spi[1] wd_spi[0] wd n/win crank default state 0 1 0 0 0 1 0 condition for default por bit description b7 wd2int - select the maximum time delay between int occurrence and int source read spi command 0 function disable. no constraint betw een int occurrence and int source read. 1 int source read must occur before the remaining of the current watchdog period plus 2 complete watchdog periods. b6, b5 mcu_oc, oc-tim - in lp v dd on, select watchdog refresh and v dd current monitoring functionality. v dd_oc_lp threshold is defined in device electrical parameters (approx 1.5 ma) in lp mode, when watchdog is not selected no watchdog + 00 in lp v dd on mode, v dd over-current has no effect no watchdog + 01 in lp v dd on mode, v dd over-current has no effect no watchdog + 10 in lp v dd on mode, v dd current > v dd_oc_lp threshold for a time > 100 ? s (typically) is a wake-up event no watchdog + 11 in lp v dd on mode, v dd current > v dd_oc_lp threshold for a time > i_mcu_oc is a wake-up ev ent. i_mcu_oc time is selected in timer register (selection range from 3.0 to 32 ms) in lp mode when watchdog is selected watchdog + 00 in lp v dd on mode, v dd current > v dd_oc_lp threshold has no effect. watchdog refresh must occur by spi command. watchdog + 01 in lp v dd on mode, v dd current > v dd_oc_lp threshold has no effect. watchdog refresh must occur by spi command. watchdog + 10 in lp v dd on mode, v dd over-current for a time > 100 ? s (typically) is a wake-up event. watchdog + 11 in lp v dd on mode, v dd current > v dd_oc_lp threshold for a time < i_mcu_oc is a watchdog refresh condition. v dd current > v dd_oc_lp threshold for a time > i_mcu_oc is a wake-up event. i_mcu_oc time is selected in timer register (selection range from 3.0 to 32 ms) b4 wd safe - select the activation of the safe pin low, at first or second c onsecutive reset pulse 0 safe pin is set low at the time of the rst pin low activation 1 safe pin is set low at the second consecutive time rst pulse b3, b2 wd_spi[1] wd_spi[0] - select the watchdog (watchdog) operation 00 simple watchdog selection: watchdog refresh done by a 8 bits or 16 bits spi 01 enhanced 1: refresh is done using the random code, and by a single 16 bits. 10 enhanced 2: refresh is done using the random code, and by two 16 bits command. 11 enhanced 4: refresh is done using the rand om code, and by four 16 bits command. b1 wd n/win - select the watchdog (watchdog) window or timeout operation 0 watchdog operation is timeout, watchdog refresh can occur anytime in the period 1 watchdog operation is window, watchdog refresh must occur in the open window (second half of period)
analog integrated circuit device data ? freescale semiconductor 71 33903/4/5 serial peripheral interface detail of control bits and register mapping b0 crank - select the v sup/1 threshold to disable v dd , while v sup1 is falling toward gnd 0 v dd disable when v sup/1 is below typically 4.0 v (parameter v sup-th1 ), and device in reset mode 1 v dd kept on when v sup/1 is below typically 4.0 v (parameter v sup_th1 ) table 19. initialization lin and i/o registers, init lin i/o (note: register can be written only in init mode) mosi first byte [15-8] [b_15 b_14] 0_0111 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 00 _ 111 p i/o-1 ovoff lin_t2[1] lin_t2[0] lin_t/1[1] lin_t/1[0] i/o-1 out-en i/o-0 out-en cyc_inv default state 0 0 0 0 0 0 0 condition for default por bit description b7 i/o-1 ovoff - select the deactivation of i/o-1 when v dd or v aux over-voltage condition is detected 0 disable i/o-1 turn off. 1 enable i/o-1 turn off, when v dd or v aux over-voltage condition is detected. b6, b5 lin_t2[1], lin_t2[0] - select pin operation as lin master pin switch or i/o 00 pin is off 01 pin operation as lin master pin switch 10 pin operation as i/o: hs switch and wake-up input 11 n/a b4, b3 lin_t/1[1], lin_t/1[0] - select pin operation as lin master pin switch or i/o 00 pin is off 01 pin operation as lin master pin switch 10 pin operation as i/o: hs switch and wake-up input 11 n/a b2 i/o-1 out-en - select the operation of the i/o-1 as output driver (hs, ls) 0 disable hs and ls drivers of pin i/o-1. i/o-1 can only be used as input. 1 enable hs and ls drivers of pin i/o-1. pin can be used as input and output driver. b1 i/o-0 out-en - select the operation of the i/o-0 as output driver (hs, ls) 0 disable hs and ls drivers of i/o-0 can only be used as input. 1 enable hs and ls drivers of the i/o-0 pin. pin can be used as input and output drivers. b0 cyc_inv - select i/o-0 operation in device lp mode, when cyclic sense is selected 0 during cyclic sense active time, i/o is set to the same state pr ior to entering in to lp mode. during cyclic sense off time, i/ o-0 is disable (hs and ls drivers off). 1 during cyclic sense active time, i/o is set to the same state prior to entering in to lp mode. during cyclic sense off time, th e opposite driver of i/ o_0 is actively set. example: if i/0_0 hs is on during active ti me, then i/o_o ls is turned on at expiration of the active time , for the duration of the cyclic sense period. bit description
analog integrated circuit device data ? 72 freescale semiconductor 33903/4/5 serial peripheral interface detail of control bits and register mapping table 20. initialization miscellaneous functions, init misc (note: register can be written only in init mode) mosi first byte [15-8] [b_15 b_14] 0_1000 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 000 p lpm w rndm spi parity int pulse int width int flash dbg res[2] dbg res[1] dbg res[0] default state 0 0 0 0 0 0 0 condition for default por bit description b7 lpm w rndm - this enables the usage of random bits 2, 1 and 0 of the mo de register to enter into lp vdd off or lp vdd on. 0 function disable: the lp mode can be entered without usage of random code 1 function enabled: the lp mode is entered using the random code b6 spi parity - select usage of the parity bit in spi write operation 0 function disable: the parity is not used. the parity bit must always set to logic 0. 1 function enable: the parity is used, and parity must be calculated. b5 int pulse - select int pin operation: low level pulse or low level 0 int pin will assert a low level pulse, duration selected by bit [b4] 1 int pin assert a permanent low level (no pulse) b4 int width - select the int pulse duration 0 int pulse duration is typically 100 ? s. ref. to dynamic parameter table for exact value. 1 int pulse duration is typically 25 ? s. ref. to dynamic parameter table for exact value. b3 int flash - select int pulse generation at 50% of the watchdog period in flash mode function disable function enable: an int pulse will occur at 50% of the watchdog period when device in flash mode. b2, b1, b0 dbg res[2], dbg res[1], dbg res[0] - allow verification of the external resistor connected at dbg pin. ref. to parametric table for resistor range value. (39) 0xx function disable 100 100 verification enable: resistor at dbg pin is typically 68 kohm (rb3) - selection of safe mode b3 101 101 verification enable: resistor at dbg pin is typically 33 kohm (rb2 - selection of safe mode b2 110 110 verification enable: resistor at dbg pin is typically 15 kohm (rb1) - selection of safe mode b1 111 111 verification enable: resistor at dbg pin is typically 0 kohm (ra) - selection of safe mode a notes 39. bits b2,1 and 0 allow the following operation: ? first , check the resistor device has detected at the debug pin. if the resistor is different, bit 5 (debug resistor) is set in inter rupt register (ref. to device flag table). ? second , over write the resistor decoded by device, to set the safe mo de operation by spi. once this function is selected by bit 2 = 1, this selection has higher priority than ?hardware?, and device will behave according to b2,b1 and b0 setting
analog integrated circuit device data ? freescale semiconductor 73 33903/4/5 serial peripheral interface detail of control bits and register mapping specific mode register the spe mode register is used for the following operation - set the device in reset mode, to exercise or test the reset functions. - go to init mode, using the secure spi command. - go to flash mode (in this mode the watchdog timer can be extended up to 32 s). - activate the safe pin by s/w. this mode (called special mode) is accessible from the secured spi command, which consist of 2 commands: 1) reading a random code and 2) then write the inverted random code plus mode selection or safe pin activation: return to init mode is done as follow (this is done from normal mode only): 1) read random code: mosi : 0001 0011 0000 0000 [hex:0x 13 00] miso report 16 bits, random code are bits (5-0) miso = xxxx xxxx xxr5 r4 r3 r2 r1 r0 (rxd = 6 bits random code) 2) write init mode + random code inverted mosi : 0101 0010 01 ri5 ri4 ri3 ri2 ri1 ri0 [hex 0x 52 hh] (r ix = random code inverted) miso : xxxx xxxx xxxx xxxx (don?t care) safe pin activation: safe pin can be set low, only in init mode, with following commands: 1) read random code: mosi : 0001 0011 0000 0000 [hex:0x 13 00] miso report 16 bits, random code are bits (5-0) miso = xxxx xxxx xxr5 r4 r3 r2 r1 r0 (rxd = 6 bits random code) 2) write init mode + random code bits 5:4 not inverted and random code bits 3:0 inverted mosi : 0101 0010 01 r5 r4 ri3 ri2 ri1 ri0 [hex 0x 52 hh] (r ix = random code inverted) miso : xxxx xxxx xxxx xxxx (don?t care) return to reset or flash mode is done similarly to the go to init mode, except that the b7 and b6 are set according to the table above (b7, b6 = 00 - go to reset, b7, b6 = 10 - go to flash). table 21. specific mode register, spe_mode mosi first byte [15-8] [b_15 b_14] 01_001 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 001 p sel_mod[1] sel_mod[0] rnd_c5b rnd_c4b rnd_c3b rnd_c2b rnd_c1b rnd_c0b default state 0 0 0 0 0 0 0 condition for default por bit description b7, b6 sel_mod[1], sel_mod[0] - mode selection: these 2 bits are used to sele ct which mode the device will enter upon a spi command. 00 reset mode 01 init mode 10 flash mode 11 n/a b5....b0 [rnd_c4b... rnd_c0b] - random code inverted, these six bits are the invert ed bits obtained from the spe mode register read command.
analog integrated circuit device data ? 74 freescale semiconductor 33903/4/5 serial peripheral interface detail of control bits and register mapping timer registers table 22. timer register a, lp v dd over-current & watchdog period normal mode, tim_a mosi first byte [15-8] [b_15 b_14] 01_010 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 010 p i_mcu[2] i_mcu[1] i_mcu[1] watchdog nor[4] w/d_n[4] w/d_nor[3] w/d_n[2] w/d_nor[0] default state 0 0 0 1 1 1 1 0 condition for default por lp v dd over-current (ms) b7 b6, b5 00 01 10 11 0 3 (def) 6 12 24 1 4 8 16 32 watchdog period in device normal mode (ms) b4, b3 b2, b1, b0 000 001 010 011 100 101 110 111 00 2.5 5 10 20 40 80 160 320 01 3 6 12 24 48 96 192 384 10 3.5 7 14 28 56 112 224 448 11 4 8 16 32 64 128 256 (def) 512 table 23. timer register b, cyclic sense an d cyclic int, in device lp mode, tim_b mosi first byte [15-8] [b_15 b_14] 01_011 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 011 p cyc-sen[3] cyc-sen[2] cyc-sen[1] cyc-sen[0] cyc-int[3] cyc-int[2] cyc-int[1] cyc-int[0] default state 0 0 0 0 0 0 0 0 condition for default por cyclic sense (ms) b7 b6, b5, b4 000 001 010 011 100 101 110 111 0 3 6 12 24 48 96 192 384 1 4 8 16 32 64 128 256 512 cyclic interrupt (ms) b3 b2, b1, b0 000 001 010 011 100 101 110 111 0 6 (def) 12 24 48 96 192 384 768 1 8 16 32 64 128 258 512 1024
analog integrated circuit device data ? freescale semiconductor 75 33903/4/5 serial peripheral interface detail of control bits and register mapping watchdog and mode registers . table 24. timer register c, watchdog lp mode or flash mode and forced wake-up timer, tim_c mosi first byte [15-8] [b_15 b_14] 01_100 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 100 p wd-lp-f[3] wd-lp-f[2] wd-lp-f[1] wd-lp-f[0] fwu[3] fwu[2] fwu[1] fwu[0] default state 0 0 0 0 0 0 0 0 condition for default por table 25. typical timing values watchdog in lp v dd on mode (ms) b7 b6, b5, b4 000 001 010 011 100 101 110 111 0 12 24 48 96 192 384 768 1536 1 16 32 64 128 256 512 1024 2048 watchdog in flash mode (ms) b7 b6, b5, b4 000 001 010 011 100 101 110 111 0 48 (def) 96 192 384 768 1536 3072 6144 1 256 512 1024 2048 4096 8192 16384 32768 forced wake-up (ms) b3 b2, b1, b0 000 001 010 011 100 101 110 111 0 48 (def) 96 192 384 768 1536 3072 6144 1 64 128 258 512 1024 2048 4096 8192 table 26. watchdog refresh register, watchdog (40) mosi first byte [15-8] [b_15 b_14] 01_101 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 101 p 0 0 0 0 0 0 0 0 default state 0 0 0 0 0 0 0 0 condition for default por notes 40. the simple watchdog refresh command is in hexadecimal: 5a00. this command is us ed to refresh the watchdog and also to transition from init mode to normal mode, and from normal request mode to normal mode (after a wake-up of a reset) table 27. mode register, mode mosi first byte [15-8] [b_15 b_14] 01_110 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 110 p mode[4] mode[3] mode[2] mode[1] mode[0] rnd_b[2] rnd_b[1] rnd_b[0] default state n/a n/a n/a n/a n/a n/a n/a n/a
analog integrated circuit device data ? 76 freescale semiconductor 33903/4/5 serial peripheral interface detail of control bits and register mapping prior to enter in lp v dd on or lp v dd off, the wake-up flags must be cleared or read. this is done by the following spi commands (see table 39, device flag, i/o real time and device identification ): 0xe100 for can wake-up clear 0xe380 for i/o wake-up clear 0xe700 for lin1 wake-up clear 0xe900 for lin2 wake-up clear if wake-up flags are not cleared, the device will enter into the selected lp mode and immediately wake-up. in addition, the can failure flags (i.e. can_f and can_uf) must be cleared in order to meet the low power current consumption specification. this is done by the following spi command: 0xe180 (read can failure flags) when the device is in lp v dd on mode, the wake-up by a spi command uses a write to ?normal request mode?, 0x5c10. mode register features the mode register includes specific functions and a ?global spi command? that allow the following: - read device current mode - read device debug status - read state of safe pin - leave debug state - release or turn off safe pin - read a 3 bit random code to enter in lp mode these global commands are built using the mode register address bit [13-9], along with several combinations of bit [15- 14] and bit [7]. note, bit [8] is always set to 1. table 28. lp v dd off selection and fwu / cyclic sense selection b7, b6, b5, b4, b3 fwu cyclic sense 0 1100 off off 0 1101 off on 0 1110 on off 0 1111 on on table 29. lp v dd on selection and operation mode b7, b6, b5, b4, b3 fwu cyclic sense cyclic int watchdog 1 0000 off off off off 1 0001 off off off on 1 0010 off off on off 1 0011 off off on on 1 0100 off on off off 1 0101 off on off on 1 0110 off on on off 1 0111 off on on on 1 1000 on off off off 1 1001 on off off on 1 1010 on off on off 1 1011 on off on on 1 1100 on on off off 1 1101 on on off on 1 1110 on on on off 1 1111 on on on on b2, b1, b0 random code inverted, these 3bits are the inverted bits obtained from the previous spi command. the usage of these bits are optional and must be pr eviously selected in the init misc register [see bit 7 (lpm w rndm) in table 20 ]
analog integrated circuit device data ? freescale semiconductor 77 33903/4/5 serial peripheral interface detail of control bits and register mapping entering into lp mode using random code - lp mode using random code must be selected in init mode via bit 7 of the init misc register. - in normal mode, read the random code using 0x1d00 or 0x1d80 command. the 3 random code bits are available on miso bits 2,1 and 0. - write lp mode by inverting the 3 random bits. example - select lp vdd off without cyclic sense and fwu: 1. in hex: 0x5c60 to enter in lp vdd off mode without using the 3 random code bits. 2. if random code is selected, the commands are: - read random code: 0x1d00 or 0x1d80, miso report in binary: bits 15- 8, bits 7-3, rnd_[2], rnd_[1], rnd_[0]. - write lp vdd off mode, using random code inverted: in binary: 0101 1100 0110 0 r nd_b[2], rnd_b[1], rnd_b[0]. table 30 summarizes these commands table 31 describes miso bits 7-0, used to decode the device?s current mode. table 32 describes the safe and debug bit decoding. table 30. device modes global commands and effects read device current mode, leave debug mode. keep safe pin as is. mosi in hexadecimal: 1d 00 mosi bits 15-14 bits 13-9 bit 8 bit 7 bits 6-0 00 01 110 1 0 000 0000 miso bit 15-8 bit 7-3 bit 2-0 fix status device current mode random code read device current mode release safe pin (turn off). mosi in hexadecimal: 1d 80 mosi bits 15-14 bits 13-9 bit 8 bit 7 bits 6-0 00 01 110 1 1 000 0000 miso bit 15-8 bit 7-3 bit 2-0 fix status device current mode random code read device current mode, leave debug mode. keep safe pin as is. mosi in hexadecimal: dd 00 miso reports debug and safe state (bits 1,0) mosi bits 15-14 bits 13-9 bit 8 bit 7 bits 6-0 11 01 110 1 0 000 0000 miso bit 15-8 bit 7-3 bit 2 bit 1 bit 0 fix status device current mode x safe debug read device current mode, keep debug mode release safe pin (turn off). mosi in hexadecimal: dd 80 miso reports debug and safe state (bits 1,0) mosi bits 15-14 bits 13-9 bit 8 bit 7 bits 6-0 11 01 110 1 1 000 0000 miso bit 15-8 bit 7-3 bit 2 bit 1 bit 0 fix status device current mode x safe debug table 31. miso bits 7-3 device current mode, any of the above commands b7, b6, b5, b4, b3 mode 0 0000 init 0 0001 flash 0 0010 normal request 0 0011 normal mode 1 xxxx low power mode ( table 29 ) table 32. safe and debug status safe and debug bits b1 description 0 safe pin off, not activated 1 safe pin on, driver activated. b0 description 0 debug mode off 1 debug mode active
analog integrated circuit device data ? 78 freescale semiconductor 33903/4/5 serial peripheral interface detail of control bits and register mapping regulator, can, i/o, int and lin registers table 33. regulator register mosi first byte [15-8] [b_15 b_14] 01_111 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 111 p v aux [1] v aux [0] - 5v-can[1] 5v-can[0] v dd bal en v dd bal auto v dd off en default state 0 0 n/a 0 0 n/a n/a n/a condition for default por por bits description b7 b6 v aux [1], v aux [0] - vauxilary regulator control 00 regulator off 01 regulator on. under-voltage (uv) and over-cur rent (oc) monitoring flags not reported. v aux is disabled when uv or oc detected after 1.0 ms blanking time. 10 regulator on. under-voltage (uv) and over-c urrent (oc) monitoring flags active. v aux is disabled when uv or oc detected after 1.0 ms blanking time. 11 regulator on. under-voltage (uv) and over-c urrent (oc) monitoring flags active. v aux is disabled when uv or oc detected after 25 ? s blanking time. b4 b3 5 v-can[1], 5 v-can[0] - 5v-can regulator control 00 regulator off 01 regulator on. thermal protection active. under-voltage (uv) and over-current (oc) monito ring flags not reported. 1.0 ms blanking time for uv and oc detection. note: by default when in debug mode 10 regulator on. thermal protection active. under-voltage (uv) and over-current (oc) m onitoring flags active. 1.0 ms blanking time for uv and oc detection. 11 regulator on. thermal protection active. under-voltage (uv) and over-current (oc) monitoring flags active after 25 ? s blanking time. b2 v dd bal en - control bit to enable the v dd external ballast transistor 0 external v dd ballast disable 1 external v dd ballast enable b1 v dd bal auto - control bit to automatically enable the v dd external ballast transistor, if v dd is > typically 60 ma 0 disable the automatic activation of the external ballast 1 enable the automatic activation of the external ballast, if v dd > typically 60 ma b0 v dd off en - control bit to allow transition into lp v dd off mode (to prevent v dd turn off) 0 disable usage of lp v dd off mode 1 enable usage of lp v dd off mode
analog integrated circuit device data ? freescale semiconductor 79 33903/4/5 serial peripheral interface detail of control bits and register mapping table 34. can register (41) mosi first byte [15-8] [b_15 b_14] 10_000 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 10_ 000p can mod[1] can mod[0] slew[1] slew[0] wake-up 1/3 - - can int default state 1 0 0 0 0 - - 0 condition for default note por por por bits description b7 b6 can mod[1], can mod[0] - can interface mode control, wake-up enable / disable 00 can interface in sleep mode, can wake-up disable. 01 can interface in receive onl y mode, can driver disable. 10 can interface is in sleep mode, can wake-up enable. in device lp mode, ? can wake-up is reported by device wake-up. in device normal mode, can wake-up reported by int. 11 can interface in transmit and receive mode. b5 b4 slew[1] slew[0] - can driver slew rate selection 00/11 fast 01 medium 10 slow b3 wake-up 1/3 - selection of can wake-up mechanism 0 3 dominant pulses wake-up mechanism 1 single dominant pulse wake-up mechanism b0 can int - select the can failure detection reporting 0 select int generation when a bus failure is fully iden tified and decoded (i.e. after 5 dominant pulses on txcan) 1 select int generation as soon as a bus failur e is detected, event if not fully identified notes 41. the first time the device is set to norm al mode, the can is in sleep wake-up enabled (bit7 = 1, bit 6 =0). the next time the device is set in normal mode, the can state is controlled by bits 7 and 6.
analog integrated circuit device data ? 80 freescale semiconductor 33903/4/5 serial peripheral interface detail of control bits and register mapping table 35. i/o register mosi first byte [15-8] [b_15 b_14] 10_001 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 10_ 001p i/o-3 [1] i/o-3 [0] i/o-2 [1] i/o-2 [0] i/o-1 [1] i/o-1 [0] i/o-0 [1] i/o-0 [0] default state 0 0 0 0 0 0 0 0 condition for default por bits description b7 b6 i/o-3 [1], i/o-3 [0] - i/o-3 pin operation 00 i/o-3 driver disable, wa ke-up capability disable 01 i/o-3 driver disable, wake-up capability enable. 10 i/o-3 hs driver enable. 11 i/o-3 hs driver enable. b5 b4 i/o-2 [1], i/o-2 [0] - i/o-2 pin operation 00 i/o-2 driver disable, wa ke-up capability disable 01 i/o-2 driver disable, wake-up capability enable. 10 i/o-2 hs driver enable. 11 i/o-2 hs driver enable. b3 b2 i/o-1 [1], i/o-1 [0] - i/o-1 pin operation 00 i/o-1 driver disable, wa ke-up capability disable 01 i/o-1 driver disable, wake-up capability enable. 10 i/o-1 ls driver enable. 11 i/o-1 hs driver enable. b1 b0 i/o-0 [1], i/o-0 [0] - i/o-0 pin operation 00 i/o-0 driver disable, wa ke-up capability disable 01 i/o-0 driver disable, wake-up capability enable. 10 i/o-0 ls driver enable. 11 i/o-0 hs driver enable.
analog integrated circuit device data ? freescale semiconductor 81 33903/4/5 serial peripheral interface detail of control bits and register mapping table 36. int register mosi first byte [15-8] [b_15 b_14] 10_010 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 10_ 010p can failure mcu req lin2 fail lin1fail i/o safe - vmon default state 0 0 0 0 0 0 0 0 condition for default por bits description b7 can failure - control bit for can failure int (canh/l to gnd, vdd or vsup, can over-current, driver over-temp, txd-pd, rxd-pr, rx2high, and canbus dominate clamp) 0 int disable 1 int enable. b6 mcu req - control bit to request an int. int will occur once when the bit is enable 0 int disable 1 int enable. b5 lin2 fail - control bit to enable int when of failure on lin2 interface 0 int disable 1 int enable. b4 lin/1 fail - control bit to enable int when of failure on lin1 interface 0 int disable 1 int enable. b3 i/o - bit to control i/o interruption: i/o failure 0 int disable 1 int enable. b2 safe - bit to enable int when of: vaux over-voltage, vdd over-voltage, vdd temp pr e-warning, vdd under-voltage (42) , safe resistor mismatch, rst termi nal short to vdd, mcu request int. (43) 0 int disable 1 int enable. b0 v mon - enable interruption by voltage monitoring of one of the voltage regulator: v aux , 5 v-can, v dd (i dd over-current, v suv , v sov , v senselow , 5v-can low or thermal shutdown, v aux low or v aux over-current 0 int disable 1 int enable. notes 42. if vdd under-voltage is set to 70% of vdd, see bits b6 and b5 in table 15 on page 69 . 43. bit 2 is used in conjunction with bi t 6. both bit 6 and bit 2 must be set to 1 to activate the mcu int request.
analog integrated circuit device data ? 82 freescale semiconductor 33903/4/5 serial peripheral interface detail of control bits and register mapping table 37. lin/1 register (45) mosi first byte [15-8] [b_15 b_14] 10_010 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 10_ 011p lin mode[1] lin mode[0] slew rate[1] slew rate[0] - lin t/1 on - v sup ext default state 0 0 0 0 0 0 0 0 condition for default por bits description b7 b6 lin mode [1], lin mode [0] - lin/1 interface mode control, wake-up enable / disable 00 lin/1 disable, wake- up capability disable 01 not used 10 lin/1 disable, wake-up capability enable 11 lin/1 transmit receive mode (44) b5 b4 slew rate[1], slew rate[0] lin/1 slew rate selection 00 slew rate for 20 kbit/s baud rate 01 slew rate for 10 kbit/s baud rate 10 slew rate for fast baud rate 11 slew rate for fast baud rate b2 lin t/1 on 0 lin/1 termination off 1 lin/1 termination on b0 v sup ext 0 lin goes recessive when device v sup/2 is below typically 6.0 v. this is to meet j2602 specification 1 lin continues operation below v sup/2 6.0 v, until 5 v-can is disabled. notes 44. the lin interface can be set in txd/rxd mode only when the txd- l input signal is in recessive state. an attempt to set txd/r xd mode, while txd-l is low, will be ignored and the lin interface remains disabled. 45. in order to use the lin interface, the 5v-can regulator must be set to on.
analog integrated circuit device data ? freescale semiconductor 83 33903/4/5 serial peripheral interface detail of control bits and register mapping table 38. lin2 register (47) mosi first byte [15-8] [b_15 b_14] 10_010 [p/n] mosi second byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 10_ 100p lin mode[1] lin mode[0] slew rate[1] slew rate[0] - lin t2 on - v sup ext default state 0 0 0 0 0 0 0 0 condition for default por bits description b7 b6 lin mode [1], lin mode [0] - lin 2 interface mode control, wake-up enable / disable 00 lin2 disable, wake- up capability disable 01 not used 10 lin2 disable, wake -up capability enable 11 lin2 transmit receive mode (46) b5 b4 slew rate[1], slew rate[0] lin 2slew rate selection 00 slew rate for 20 kbit/s baud rate 01 slew rate for 10 kbit/s baud rate 10 slew rate for fast baud rate 11 slew rate for fast baud rate b2 lin t2 on 0 lin 2 termination off 1 lin 2 termination on b0 v sup ext 0 lin goes recessive when device v sup/2 is below typically 6.0 v. this is to meet j2602 specification 1 lin continues operation below v sup/2 6.0 v, until 5 v-can is disabled. notes 46. the lin interface can be set in txd/rxd mode only when the txd-l input signal is in a recessive state. an attempt to set txd /rxd mode while txd-l is low, will be ignored a nd the lin interface will remain disabled. 47. in order to use the lin interface, the 5v-can regulator must be set to on.
analog integrated circuit device data ? 84 freescale semiconductor 33903/4/5 serial peripheral interface flags and device status flags and device status description the table below is a summary of the device flags, i/o real time level, device identificati on, and includes examples of spi commands (spi commands do not use parity functions). they are obtained using the following commands. this command is composed of the following: bits 15 and 14: ? [1 1] for failure flags ? - [0 0] for i/o real time st atus, device identification and can lin driver receiver real time state. ? bit 13 to 9 are the register address from which the flags is to be read. ?bit 8 = 1 (this is not parity bit function, as this is a read command). when a failure event occurs, the respective flag is set and remains latched until it is cleared by a read command (provided the failure event has recovered). table 39. device flag, i/o real time and device identification bits 15-14 13-9 8 7 6 5 4 3 2 1 0 mosi mosi bits 15-7 next 7 mosi bits (bits 6.0) should be ?000_0000? bits [15, 14] address [13-9] bit 8 bit 7 miso 8 bits device fixed status (bits 15...8) miso bits [7-0], devi ce response on miso pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reg 11 0_1111 reg 1 0 v aux_low v aux_over- current 5v -can_ thermal shutdown 5v -can_ uv 5v -can_ over- current v sense_ low v sup_ under- voltage i dd-oc- normal mode 11 1 - - - v dd_ thermal shutdown r st_low (<100 ms) v sup_ batfail i dd-oc-lp v dd on mode hexa spi commands to get vreg flags: mosi 0x df 00, and mosi ox df 80 can 11 1_0000 can 1 0 can wake-up - can over- temp rxd low (48) rxd high txd dom bus dom clamp can over- current 1 can_uf can_f canl to v bat canl to v dd canl to gnd canh to v bat canh to v dd canh to gnd hexa spi commands to get can flags: mosi 0x e1 00, and mosi 0x e1 80 00 1_0000 can 1 1 can driver state can receiver state can wu en/dis - - - - - hexa spi commands to get can real time status: mosi 0x 21 80 i/o 11 1_0001 i/o 1 0 hs3 short to gnd hs2 short to gnd spi parity error csb low >2.0 ms v sup/2-uv v sup/1-ov i/o_o thermal watchdog flash mode 50% 1 i/o_1-3 wake-up i/o_0-2 wake-up spi wake-up fwu int service timeout lp v dd off reset request hardware leave debug hexa spi commands to get i/o flags and i/o wake-up: mosi 0x e3 00, and mosi 0x e3 80 00 1_0001 i/o 1 1 i/o_3 state i/o_2 state i/o_1 state i/o_0 state hexa spi commands to get i/o real time level: mosi 0x 23 80 safe 11 1_0010 safe 1 0 int request rst high dbg resistor v dd temp pre-warning v dd uv v dd over- voltage v aux_over- voltage - 1 - - - v dd low >100 ms v dd low rst rst low >100 ms multiple resets watchdog refresh failure hexa spi commands to get int and rst flags: mosi 0x e5 00, and mosi 0x e5 80 00 1_0010 safe 1 1 v dd (5.0 v or 3.3 v) device p/n 1 device p/n 0 id4 id3 id2 id1 id0 hexa spi commands to get device identification: mosi 0x 2580 example: miso bit [7-0] = 1011 0100: mc33904, 5.0 v version, silicon rev. c (pass 3.3)
analog integrated circuit device data ? freescale semiconductor 85 33903/4/5 serial peripheral interface flags and device status lin/1 11 1_0011 lin 1 1 0 - lin1 wake-up lin1 term short to gnd lin 1 over-temp rxd1 low rxd1 high txd1 dom lin1 bus dom clamp hexa spi commands to get lin 2 flags: mosi 0x e7 00 00 1_0011 lin 1 1 1 lin1 state lin1 wu en/dis - - - - - - hexa spi commands to get lin1 real time status: mosi 0x 27 80 lin2 11 1_0100 lin 2 1 0 - lin2 wake-up lin2 term short to gnd lin 2 over-temp rxd2 low rxd2 high txd2 dom lin2 bus dom clamp hexa spi commands to get lin 2 flags: mosi 0x e9 00 00 1_0100 lin 2 1 1 lin2 state lin2 wu en/dis - - - - - - hexa spi commands to get lin2 real time status: mosi 0x 29 80 notes 48. not available on ?c? versions table 40. flag descriptions flag description reg v aux_low description reports that v aux regulator output voltage is lower than the v aux _ uv threshold. set / reset condition set: v aux below threshold for t >100 ? s typically. reset: v aux above threshold and flag read (spi) v aux_over- current description report that current out of v aux regulator is above v aux_oc threshold. set / reset condition set: current above threshold for t >100 ? s. reset: current below threshold and flag read by spi. 5 v -can_ thermal shutdown description report that the 5 v-can regulator has reached over-temperature threshold. set / reset condition set: 5 v-can thermal sensor above threshold. reset: thermal sensor below threshold and flag read (spi) 5v -can_uv description reports that 5 v - can regulator output voltage is lower than the 5 v -can uv threshold. set / reset condition set: 5v-can below 5v -can uv for t >100 ? s typically. reset: 5v-can > threshold and flag read (spi) 5v-can_ over-current description report that the can driver output current is above threshold. set / reset condition set: 5v-can current above threshold for t>100 ? s. reset: 5v-can current below threshold and flag read (spi) v sense_ low description reports that vsense pin is lower than the v sense low threshold. set / reset condition set: vsense below threshold for t >100 ? s typically. reset: v sense above threshold and flag read (spi) v sup_ under- voltage description reports that vsup/1 pin is lower than the v s1_low threshold. set / reset condition set: v sup/1 below threshold for t >100 ? s typically. reset: v sup/1 above threshold and flag read (spi) i dd-oc- normal mode description report that current out of vdd pin is higher that i dd-oc threshold, while device is in normal mode. set / reset condition set: current above threshold for t>100 ? s typically. reset; current below threshold and flag read (spi) v dd_ thermal shutdown description report that the v dd has reached over-temperature threshold, and was turned off. set / reset condition set: v dd off due to thermal condition. reset: v dd recover and flag read (spi) r st_low (<100 ms) description report that the rst pin has detected a low level, shorter than 100 ms set / reset condition set: after detection of reset low pulse. reset: reset pulse terminated and flag read (spi) v sup_ batfail description report that the device voltage at vsup/1 pin was below batfail threshold. set / reset condition set: v sup/1 below batfail. reset: v sup/1 above threshold, and flag read (spi) i dd-oc-lp v dd on mode description report that current out of vdd pin is higher that i dd-oc threshold lp, while device is in lp v dd on mode. set / reset condition set: current above threshold for t>100 ? s typically. reset; current below threshold and flag read (spi) table 39. device flag, i/o real time and device identification
analog integrated circuit device data ? 86 freescale semiconductor 33903/4/5 serial peripheral interface flags and device status can can driver state description report real time can bus driver state: 1 if driver is enable, 0 if driver disable set / reset condition set: can driver is enable. reset: can driver is disable. driver can be disable by spi command (ex can set in rxd only mode) or following a failur e event (ex: txd dominant). flag read spi command (0x2180) do not clear the flag, as it is ?real time? information. can receiver state description report real time can bus receiver state: 1 if enable, 0 if disable set / reset condition set: can bus receiver is enable. reset: can bus re ceiver is disable. re ceiver disable by spi command (ex: can set in sleep mode). flag read spi command (0x2180) do not clear the flag, as it is ?real time? information. can wu enable description report real time can bus wake-up receiver stat e: 1 if wu receiver is enable, 0 if disable set / reset condition set: can wake-up receiver is enable. reset: can wake -up receiver is disable. wake-up receiver is controlled by spi, and is active by default af ter device power on. spi command (0x2180) do not change flag state. can wake-up description report that wake-up source is can set / reset condition set: after can wake detected. reset: flag read (spi) can over- temp description report that the can interface has reach over-temperature threshold. set / reset condition set: can thermal sensor above threshold. reset: t hermal sensor below threshold and flag read (spi) rxd low (49) description report that rxd pin is shorted to gnd. set / reset condition set: rxd low failure detected. reset: failure recovered and flag read (spi) rxd high description report that rxd pin is shorted to recessive voltage. set / reset condition set: rxd high failure detected. reset: failure recovered and flag read (spi) txd dom description report that txd pin is shorted to gnd. set / reset condition set: txd low failure detected. reset: failure recovered and flag read (spi) bus dom clamp description report that the can bus is dominant for a time longer than t dom set / reset condition set: bus dominant clamp failure detected. reset: failure recovered and flag read (spi) can over- current description report that the can current is above can over-current threshold. set / reset condition set: can current above threshold. reset: current below threshold and flag read (spi) can_uf description report that the can failure detection has not yet identified the bus failure set / reset condition set: bus failure pre detection. reset: can bus failure recovered and flag read can_f description report that the can failure detection has identified the bus failure set / reset condition set: bus failure complete detetction.reset: can bus failure recovered and flag read canl to v bat description report can l short to v bat failure set / reset condition set: failure detected. reset failure recovered and flag read (spi) canl to vdd description report canl short to vdd set / reset condition set: failure detected. reset failure recovered and flag read (spi) canl to gnd description report can l short to gnd failure set / reset condition set: failure detected. reset failure recovered and flag read (spi) canh to v bat description report can h short to v bat failure set / reset condition set: failure detected. reset failure recovered and flag read (spi) canh to vdd description report canh short to vdd set / reset condition set: failure detected. reset failure recovered and flag read (spi) canh to gnd description report can h short to gnd failure set / reset condition set: failure detected. reset failure recovered and flag read (spi) notes 49. not available on ?c? versions table 40. flag descriptions flag description
analog integrated circuit device data ? freescale semiconductor 87 33903/4/5 serial peripheral interface flags and device status i/o hs3 short to gnd description report i/o-3 hs switch short to gnd failure set / reset condition set: failure detected. reset failure recovered and flag read (spi) hs2 short to gnd description report i/o-2 hs switch short to gnd failure set / reset condition set: failure detected. reset failure recovered and flag read (spi) spi parity error description report spi parity error was detected. set / reset condition set: failure detected. reset: flag read (spi) csb low >2.0 ms description report spi csb was low for a time longer than typically 2.0 ms set / reset condition set: failure detected. reset: flag read (spi) v sup/2-uv description report that v sup/2 is below v s2_low threshold. set / reset condition set v sup/2 below v s2_low thresh. reset v sup/2 > v s2_low thresh and flag read (spi) v sup/1-ov description report that v sup/1 is above v s_high threshold. set / reset condition set v sup/1 above v s_high threshold. reset v sup/1 < v s_high thresh and flag read (spi) i/o-0 thermal description report that the i/o-0 hs switch has reach over-temperature threshold. set / reset condition set: i/o-0 hs switch thermal sensor above threshol d. reset: thermal sensor below threshold and flag read (spi) watchdog flash mode 50% description report that the watchdog period has reach 50% of its value, while device is in flash mode. set / reset condition set: watchdog period > 50%. reset: flag read i/o-1-3 wake- up description report that wake-up sour ce is i/o-1 or i/o-3 set / reset condition set: after i/o-1 or i/o-3 wake detected. reset: flag read (spi) i/o-0-2 wake- up description report that wake-up sour ce is i/o-0 or i/o-2 set / reset condition set: after i/o-0 or i/o-2 wake detected. reset: flag read (spi) spi wake-up description report that wake-up source is spi command, in lp v dd on mode. set / reset condition set: after spi wake-up detected. reset: flag read (spi) fwu description report that wake-up source is forced wake-up set / reset condition set: after forced wake-up detected. reset: flag read (spi) int service timeout description report that int timeout error detected. set / reset condition set: int service timeout expired. reset: flag read. lp v dd off description report that lp v dd off mode was selected, prior wake-up occurred. set / reset condition set: lp v dd off selected. reset: flag read (spi) reset request description report that rst source is an request from a spi command (go to rst mode). set / reset condition set: after reset occurred due to spi request. reset: flag read (spi) hardware leave debug description report that the device left the debug mode due to hardware cause (voltage at dbg pin lower than typically 8.0 v). set / reset condition set: device leave debug mode due to hardware cause. reset: flag read. table 40. flag descriptions flag description
analog integrated circuit device data ? 88 freescale semiconductor 33903/4/5 serial peripheral interface flags and device status int int request description report that int source is an int request from a spi command. set / reset condition set: int occurred. reset: flag read (spi) rst high description report that rst pin is shorted to high voltage. set / reset condition set: rst failure detection. reset: flag read. dbg resistor description report that the resistor at dbg pin is different fr om expected (different from spi register content). set / reset condition set: failure detected. reset: correct resistor and flag read (spi). v dd temp pre- warning description report that the v dd has reached over-temperature pre-warning threshold. set / reset condition set: v dd thermal sensor above threshold. reset: v dd thermal sensor below threshold and flag read (spi) v dd uv description reports that vdd pin is lower than the v dduv threshold. set / reset condition set: vdd below threshold for t >100 ? s typically. reset: v dd above threshold and flag read (spi) v dd over- voltage description reports that vdd pin is higher than the typically v dd + 0.6 v threshold. i/o-1 can be turned off if this function is selected in init register. set / reset condition set: vdd above threshold for t >100 ? s typically. reset: v dd below threshold and flag read (spi) v aux_over- voltage description reports that vaux pin is hi gher than the typically v aux + 0.6 v threshold. i/o-1 can be turned off if this function is selected in init register. set / reset condition set: v aux above threshold for t >100 ? s typically. reset: v aux below threshold and flag read (spi) v dd low >100 ms description reports that vdd pin is lower than the vdd uv threshold for a time longer than 100 ms set / reset condition set: vdd below threshold for t >100 ms typically. reset: v dd above threshold and flag read (spi) v dd low description report that v dd is below v dd under-voltage threshold. set / reset condition set: v dd below threshold. reset: fag read (spi) v dd (5.0 v or 3.3 v) description 0: mean 3.3 v v dd version 1: mean 5.0 v v d d version set / reset condition n/a device p/n1 and 0 description describe the device part number: 00: mc33903 01: mc33904 10: mc33905s 11: mc333905d set / reset condition n/a device id 4 to 0 description describe the silicon revision number 10010: silicon revision a (pass 3.1) 10011: silicon revision b (pass 3.2) 10100: silicon revision c (pass 3.3) set / reset condition n/a rst low >100 ms description report that the rst pin has detected a low level, longer than 100 ms (reset permanent low) set / reset condition set: after detection of reset low pulse. reset: reset pulse terminated and flag read (spi) multiple resets description report that the more than 8 consecutive reset pulses occurred, due to missing or wrong watchdog refresh. set / reset condition set: after detection of multiple reset pulses. reset: flag read (spi) watchdog refresh failure description report that a wrong or missing watchdog failure occurred. set / reset condition set: failure detected. reset: flag read (spi) table 40. flag descriptions flag description
analog integrated circuit device data ? freescale semiconductor 89 33903/4/5 serial peripheral interface flags and device status lin/1/2 lin/1/2 bus dom clamp description report that the lin/1/2 bus is dominant for a time longer than t dom set / reset condition set: bus dominant clamp failure detected. reset: failure recovered and flag read (spi) lin/1/2 state description report real time lin interface txd/rxd mode. 1 if lin is in txd/rxd mode. 0 is lin is not in txd/ rxd mode. set / reset condition set: lin in txd rxd mode. reset: lin not in txd/rxd mode. lin not in txd/rxd mode by spi command (ex lin set in sleep mode) or following a failure event (ex: txl dominant). flag read spi command (0x2780 or 0x2980) do not clear it, as it is ?real time? flag. lin/1/2 wu description report real time lin wake-up receiver state. 1 if lin wake-up is enable, 0 if lin wake-up is disable (means lin signal will not be detected and will not wake-up the device). set / reset condition set: lin wu enable (lin interface set in sleep mode wake-up enable). reset: lin wake-up disable (lin interface set in sleep mode wake-up dis able). flag read spi command (0x2780 or 0x2980) do not clear the flag, as it is ?real time? information. lin/1/2 wake-up description report that wake-up source is lin/1/2 set / reset condition set: after lin/1/2 wake detected. reset: flag read (spi) lin/1/2 term short to gnd description report lin/1/2 short to gnd failure set / reset condition set: failure detected. reset failure recovered and flag read (spi) lin/1/2 over-temp description report that the lin/1/2 interface has reach over-temperature threshold. set / reset condition set: lin/1/2 thermal sensor above threshold. reset: sensor below threshold and flag read (spi) rxd-l/1/2 low description report that rxd/1/2 pin is shorted to gnd. set / reset condition set: rxd low failure detected. reset: failure recovered and flag read (spi) rxd-l/1/2 high description report that rxd/1/2pin is shorted to recessive voltage. set / reset condition set: rxd high failure detected. reset: failure recovered and flag read (spi) txd-l/1/2 dom description report that txd/1/2 pin is shorted to gnd. set / reset condition set: txd low failure detected. reset: failure recovered and flag read (spi) table 40. flag descriptions flag description
analog integrated circuit device data ? 90 freescale semiconductor 33903/4/5 serial peripheral interface flags and device status fix and extended device status for every spi command, the device response on miso is fixed status information. this information is either: two bytes fix status + extended stat us: when a device write command is used (mosi bits 15-14, bits c1 c0 = 01) one byte fix status: when a device read operation is performed (mosi bits 15-14, bits c1 c0 = 00 or 11). table 41. status bits description bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 miso int wu rst can-g lin-g i/o-g safe-g vreg-g can-bus can-loc lin2 lin1 i/o-1 i/o-0 vreg-1 vreg-0 bits description int indicates that an int has occurred and that int flags are pending to be read. wu indicates that a wake-up has occurred and that wake-up flags are pending to be read. rst indicates that a reset has occurred and that the flags that report the reset source are pending to be read. can-g the int, wu, or rst source is can interface. can local or can bus source. lin-g the int, wu, or rst source is lin2 or lin1 interface i/o-g the int, wu, or rst source is i/o interfaces. safe-g the int, wu, or rst source is from a safe condition vreg-g the int, wu, or rst source is from a r egulator event, or voltage monitoring event can-loc the int, wu, or rst source is can interface. can local source. can-bus the int, wu, or rst source is can interface. can bus source. lin2 the int, wu, or rst source is lin2 interface lin/lin1 the int, wu, or rst source is lin1 interface i/o-0 the int, wu, or rst source is i/o interf ace, flag from i/o sub adress low (bit 7 = 0) i/o-1 the int, wu, or rst source is i/o interf ace, flag from i/o sub adress high (bit 7 = 1) vreg-1 the int, wu, or rst source is from a regulator event, flag from reg register sub adress high (bit 7 = 1) vreg-0 the int, wu, or rst source is from a regulator event, flag from reg register sub adress low (bit 7 = 0)
analog integrated circuit device data ? freescale semiconductor 91 33903/4/5 typical applications typical applications figure 42. 33905d typical application schematic cs sclk mosi int 5v-can miso rxd txd gnd rst v dd v sup2 i/o-1 canl canh split i/o-0 ve mcu v bat q1 d1 safe circuitry v bat can bus v baux v aux safe mux a/d spi can v sense v sup1 q2 v caux v sup v sup v sup v sup v dd int rst rf module switch detection interface can xcvr safing micro controller 5.0 v (3.3 v) dbg v b eswitch rxd-l1 txd-l1 lin1 rxd-l2 txd-l2 lin2 1.0 k 22 k 100 nf 100 nf 100 nf 22 ? f >4.7 ? f >2.2 ? f 4.7 nf <10 k 4.7 k * 60 60 * optional * notes 50. tested per specific oem emc requirements for can and lin with additional capacitor > 10 ? f on vsup1/vsup2 pins (50) lin1 lin term1 lin bus 1 1.0 k 1.0 k vsup1/2 option 1 option 2 lin2 lin term2 lin bus 1 1.0 k 1.0 k vsup1/2 option 1 option 2 >1.0 ? f n/c
analog integrated circuit device data ? 92 freescale semiconductor 33903/4/5 typical applications figure 43. 33905s typical application schematic cs sclk mosi int 5v-can miso rxd txd gnd rst vdd vsup2 i/o-1 canl canh split i/o-0 ve mcu v bat q1* d1 safe circuitry v bat can bus vbaux vaux safe mux a/d spi can vsense vsup1 q2 vcaux v sup v sup v sup v sup v dd int rst rf module switch detection interface can xcvr safing micro controller 5.0 v (3.3 v) dbg vb eswitch rxd-l1 txd-l1 lin1 i/o-3 v sup 1.0 k 22 k 100 nf 100 nf 100 nf 22 ? f >1.0 ? f >4.7 ? f >2.2 ? f 4.7 nf <10 k 4.7 k * 60 60 (51) notes 51. tested per specific oem emc requirements for can and lin with additional capacitor > 10 ? f on vsup1/vsup2 pins lin1 lin term1 lin bus 1 1.0 k 1.0 k vsup1/2 option 1 option 2
analog integrated circuit device data ? freescale semiconductor 93 33903/4/5 typical applications figure 44. 33904 typical application schematic cs sclk mosi int 5v-can miso rxd txd gnd rst vdd vsup2 i/o-1 canl canh dbg split i/o-0 ve vb mcu v bat q1* d1 safe circuitry v bat can bus vbaux vaux safe mux a/d spi can vsense vsup1 q2 vcaux v sup v sup or v sup v sup v dd int rst rf module switch detection interface can xcvr function eswitch safing micro controller 5v (3.3 v) i/o-3 i/o-2 v sup v bat 1.0 k 22 k 100 nf 100nf 100 nf 22 ? f >4.7 ? f >2.2 ? f 4.7 nf <10 k 4.7 k * 60 60 100 nf * optional 22 k (52) notes 52. tested per specific oem emc requirements for can and lin with additional capacitor > 10 ? f on vsup1/vsup2 pins >1.0 ? f n/c
analog integrated circuit device data ? 94 freescale semiconductor 33903/4/5 typical applications figure 45. 33903 typical application schematic cs sclk mosi int 5v-can miso rxd txd gnd rst vdd canl canh dbg split i/o-0 mcu safe circuitry v bat can bus safe spi can or v sup v sup v dd int rst function 22 k 100 nf >1.0 ? f >4.7 ? f 4.7 nf 60 60 (53) notes 53. tested per specific oem emc requirements for can and lin with additional capacitor > 10 ? f on vsup1/vsup2 pins vsup1 v bat d1 v sup 100 nf 22 ? f vsup2 n/c
analog integrated circuit device data ? freescale semiconductor 95 33903/4/5 typical applications figure 46. 33903d typical application schematic cs sclk mosi int 5v-can miso rxd txd gnd rst vdd vsup canl canh split io-0 ve mcu v bat q1 d1 safe circuitry v bat can bus safe mux a/d spi can vsense v sup v sup v sup v dd int rst dbg vb rxd-l1 txd-l1 lin1 rxd-l2 txd-l2 lin2 lin bus 1 lin1 lin-t1 1.0 k 1.0 k 22 k 100 nf 100 nf 100 nf 22 ? f >1.0 ? f >4.7 ? f 4.7 nf 4.7 k (optional) 60 60 * = optional * 1.0 k option1 option2 lin bus 2 lin2 lin-t2 1.0 k 1.0 k option1 option2 vsup vsup notes 54. tested per specific oem emc requirements for can and lin with additional capacitor > 10 ? f on vsup pin
analog integrated circuit device data ? 96 freescale semiconductor 33903/4/5 typical applications figure 47. 33903s typical application schematic cs sclk mosi int 5v-can miso rxd txd gnd rst vdd vsup canl canh split ve mcu v bat q1 d1 safe circuitry v bat can bus safe mux a/d spi can vsense v sup v sup v sup v dd int rst dbg vb rxd-l txd-l lin lin bus lin lin-t 1.0 k 1.0 k 22 k 100 nf 100 nf 100 nf 22 ? f >1.0 ? f >4.7 ? f 4.7 nf 4.7 k (optional) 60 60 * = optional * 1.0 k option1 option2 vsup notes 55. tested per specific oem emc requirements for can and lin with additional capacitor > 10 ? f on vsup pin 56. leave n/c pins open. io-3 v sup io-0 n/c
analog integrated circuit device data ? freescale semiconductor 97 33903/4/5 typical applications figure 48. 33903p typical application schematic cs sclk mosi int 5v-can miso rxd txd gnd rst vdd vsup canl canh split ve mcu v bat q1 d1 safe circuitry v bat can bus safe mux a/d spi can vsense v sup v sup v sup v dd int rst dbg vb 1.0 k 22 k 100 nf 100 nf 100 nf 22 ? f >1.0 ? f >4.7 ? f 4.7 nf 4.7 k (optional) 60 60 * = optional * notes 57. tested per specific oem emc requirements for can and lin with additional capacitor > 10 ? f on vsup pin 58. leave n/c pins open. io-3 v sup io-0 n/c i/o-2 v bat 100 nf 22 k
analog integrated circuit device data ? 98 freescale semiconductor 33903/4/5 typical applications the following figure illustrates the application case where two reverse battery diodes can be used for optimization of the filtering and buffering capacitor at the vdd pin. this allows using a minimum value capacitor at the vdd pin to guarantee reset-free operation of the mcu during the cranking pulse and temporary (50 ms) loss of the v bat supply. applications without an external ballast on v dd and without using the vaux regulator are illustrated as well. figure 49. application options ex2: split v sup supply ex 4: no external transistor - no vaux ex 3: no external transistor, v dd ~100 ma capability ex1: single v sup supply optimized solution for cranking pulses. c1 is sized for mcu power supply buffer only. vdd vsup2 ve vb v bat q1 d1 vbaux vaux 5.0 v/3.3 v vsup1 q2 partial view vdd ve vb v bat d1 vbaux vdd ve vb v bat d1 vdd ve vb v bat q1 d2 vsup2 vsup1 vsup2 vsup1 vsup2 vsup1 d1 c1 c2 vcaux q2 vaux vcaux q2 vbaux vaux vcaux vbaux vaux vcaux partial view partial view partial view 5.0 v/3.3 v 5.0 v/3.3 v delivered by internal path transistor.
analog integrated circuit device data ? freescale semiconductor 99 33903/4/5 packaging soic 32 package dimensions packaging soic 32 package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. ek suffix (pb-free) 32-pin soic wide body exposed pad 98asa10556d revision d
analog integrated circuit device data ? 100 freescale semiconductor 33903/4/5 packaging soic 32 package dimensions ek suffix (pb-free) 32-pin soic wide body exposed pad 98asa10556d revision d
analog integrated circuit device data ? freescale semiconductor 101 33903/4/5 packaging soic 32 package dimensions ek suffix (pb-free) 32-pin soic wide body exposed pad 98asa10556d revision d
analog integrated circuit device data ? 102 freescale semiconductor 33903/4/5 packaging soic 54 package dimensions soic 54 package dimensions ek suffix (pb-free) 54-pin soic wide body exposed pad 98asa10506d revision d
analog integrated circuit device data ? freescale semiconductor 103 33903/4/5 packaging soic 54 package dimensions ek suffix (pb-free) 54-pin soic wide body exposed pad 98asa10506d revision d
analog integrated circuit device data ? 104 freescale semiconductor 33903/4/5 packaging soic 54 package dimensions ek suffix (pb-free) 54-pin soic wide body exposed pad 98asa10506d revision d
analog integrated circuit device data ? freescale semiconductor 105 33903/4/5 revision history revision history revision date description of changes 4.0 9/2010 ? initial release - this document supersedes document mc33904_5. ? initial release of document in cludes the mc33903 part number, the vdd 3.3 v version description, and the silicon revision rev. 3.2. change details available upon request. 5.0 12/2010 ? added cyclic int operation during lp vdd on mode 48 ? changed vsup pin to vsup1 and pin 2 (nc) to vsup2 for the 33903 device ? removed drop voltage without external pnp pass transistor (19) 20 for v dd =3.3 v devices ? added v sup1-3.3 to vdd voltage regulator, vdd pin 20 . ? added pull-up current, txd, vin = 0 v 24 for v dd =3.3 v devices ?revised mux and ram registers 67 ?revised status bits description 90 ? added entering into lp mode using random code 77 . 6.0 4/2011 ? removed part numbers mcz33905s3ek/r2, mcz33904a3ek/r2 and mcz33905d3ek/r2, and added part numbers mcz33903bd3ek/r2, mcz33903bd5ek/r2, mcz33903bs3ek/r2 and mcz33903bs5ek/r2. ? voltage supply was improved from 27v to 28v. ? changed classification from advance information to technical data. ? updated notes in tables 8 . ?revised tables 8 ; attenuation/gain ratio for i/o -0 and i/o-1 actual voltage: to reflect a typical value. ? corrected typographical errors throughout. ? added chip temperature: mux-out voltage ( guaranteed by design and characterization) parameter to tables 8 . ? updated i/o pins (i/o-0: i/o-3) on page 36 . 7.0 9/2011 ? updated vout-3.3 maximum ? updated t lead parameter ? added t cs low parameter ? updated the detail operation section to reflect the importance of acknowledging t lead and t cs low . ? corrected typographical error in tables 34 can register for slew rate bits b5,b4 8.0 1/2011 ? added 12 pcz devices to the ordering information ? bit label change on table 39 from int to safe ? revised notes on table 1 to include ?c? version ?split falling edge of cs to rising edge of sclk to differentiate the ?c? version ? added ?c? version note to table 39 and table 40 ? added device id 10100 rev c, pass 3.3 to device id 4 to 0 ? added debug mode dbg voltage range parameter. already detailed in text. ? added the mc33903p device, making additions throughout the document, where applicable. 9.0 2/2012 ? changed all pc devices to mc devices.
how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road ? tempe, arizona 85284 ? 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. ? headquarters ? arco tower 15f ? 1-8-1, shimo-meguro, meguro-ku, ? tokyo 153-0064 ? japan ? 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. ? exchange building 23f ? no. 118 jianguo road ? chaoyang district ? beijing 100022 ? china ? +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com freescale and the freescale logo are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. qorivva, s12 magniv, smartmos and xtrinsic are trademarks of freescale semiconductor, inc. arm is the registered trademark of arm limited. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. all other product or service names are the property of their respective owners. ?2012 freescale semiconductor, inc. mc33903_4_5 rev. 9.0 2/2012 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further to products herein. freescale semiconductor makes no warranty, representation or regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, be validated for each customer application by technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part.

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